Search

Tuan A. Hoang

Examiner (ID: 7516, Phone: (571)270-0406 , Office: P/2896 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2896, 2898
Total Applications
557
Issued Applications
368
Pending Applications
78
Abandoned Applications
131

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20230495 [patent_doc_number] => 12419161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Display apparatus and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/722572 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3321 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722572
Display apparatus and method of manufacturing the same Apr 17, 2022 Issued
Array ( [id] => 18712949 [patent_doc_number] => 20230335582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => MEMORY DEVICE ISOLATION STRUCTURE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/720122 [patent_app_country] => US [patent_app_date] => 2022-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/720122
MEMORY DEVICE ISOLATION STRUCTURE AND METHOD Apr 12, 2022 Pending
Array ( [id] => 19277473 [patent_doc_number] => 12027606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Semiconductor devices with air gate spacer and air gate cap [patent_app_type] => utility [patent_app_number] => 17/717684 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 51 [patent_no_of_words] => 10496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17717684 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/717684
Semiconductor devices with air gate spacer and air gate cap Apr 10, 2022 Issued
Array ( [id] => 18680136 [patent_doc_number] => 20230317794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => ULTRA-SCALED TRANSISTOR DEVICES TO ENABLE CELL SIZE SCALING [patent_app_type] => utility [patent_app_number] => 17/712057 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712057 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712057
ULTRA-SCALED TRANSISTOR DEVICES TO ENABLE CELL SIZE SCALING Mar 31, 2022 Pending
Array ( [id] => 18679492 [patent_doc_number] => 20230317148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => EPITAXIAL LAYERS OF A TRANSISTOR ELECTRICALLY COUPLED WITH A BACKSIDE CONTACT METAL [patent_app_type] => utility [patent_app_number] => 17/710942 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/710942
EPITAXIAL LAYERS OF A TRANSISTOR ELECTRICALLY COUPLED WITH A BACKSIDE CONTACT METAL Mar 30, 2022 Pending
Array ( [id] => 19018163 [patent_doc_number] => 11925125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => High retention storage layer using ultra-low RA MgO process in perpendicular magnetic tunnel junctions for MRAM devices [patent_app_type] => utility [patent_app_number] => 17/581950 [patent_app_country] => US [patent_app_date] => 2022-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3947 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581950 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581950
High retention storage layer using ultra-low RA MgO process in perpendicular magnetic tunnel junctions for MRAM devices Jan 22, 2022 Issued
Array ( [id] => 19169961 [patent_doc_number] => 11985887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Systems and methods for supporting and conveying a substrate [patent_app_type] => utility [patent_app_number] => 17/647410 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 25527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647410 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647410
Systems and methods for supporting and conveying a substrate Jan 6, 2022 Issued
Array ( [id] => 17551491 [patent_doc_number] => 20220122833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 17/568072 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568072 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568072
Method of manufacturing semiconductor device, recording medium, and substrate processing method Jan 3, 2022 Issued
Array ( [id] => 19584165 [patent_doc_number] => 12150312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Array of capacitors, array of memory cells, methods of forming an array of capacitors, and methods of forming an array of memory cells [patent_app_type] => utility [patent_app_number] => 17/567268 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 5941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567268 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567268
Array of capacitors, array of memory cells, methods of forming an array of capacitors, and methods of forming an array of memory cells Jan 2, 2022 Issued
Array ( [id] => 19936950 [patent_doc_number] => 12310171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Organic light emitting display device [patent_app_type] => utility [patent_app_number] => 17/567804 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 11926 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567804 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567804
Organic light emitting display device Jan 2, 2022 Issued
Array ( [id] => 17536624 [patent_doc_number] => 20220115233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => LASER IRRADIATION METHOD AND LASER IRRADIATION APPARATUS [patent_app_type] => utility [patent_app_number] => 17/559415 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559415
Laser irradiation method and laser irradiation apparatus Dec 21, 2021 Issued
Array ( [id] => 17523117 [patent_doc_number] => 20220108966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/552550 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552550 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552550
Semiconductor device Dec 15, 2021 Issued
Array ( [id] => 17661102 [patent_doc_number] => 20220181567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => SOLID-STATE IMAGING ELEMENT, PRODUCTION METHOD THEREOF, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/550897 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550897 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550897
Solid-state imaging element, production method thereof, and electronic device Dec 13, 2021 Issued
Array ( [id] => 17486123 [patent_doc_number] => 20220093627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => STAIRCASE PATTERNING FOR 3D NAND DEVICES [patent_app_type] => utility [patent_app_number] => 17/543235 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543235 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543235
Staircase patterning for 3D NAND devices Dec 5, 2021 Issued
Array ( [id] => 18394947 [patent_doc_number] => 20230163168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => FORKSHEET TRANSISTOR DEVICE WITH AIR GAP SPINE [patent_app_type] => utility [patent_app_number] => 17/455938 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455938
FORKSHEET TRANSISTOR DEVICE WITH AIR GAP SPINE Nov 21, 2021 Issued
Array ( [id] => 17431976 [patent_doc_number] => 20220059685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => Cut-Fin Isolation Regions and Method Forming Same [patent_app_type] => utility [patent_app_number] => 17/453869 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453869
Cut-fin isolation regions and method forming same Nov 7, 2021 Issued
Array ( [id] => 18360125 [patent_doc_number] => 20230141716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => FINFETS HAVING VARIOUS DIFFERENT THICKNESSES OF GATE OXIDES AND RELATED APPARATUS, METHODS, AND COMPUTING SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/453727 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453727 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453727
Apparatuses including Finfets having different gate oxide configurations, and related computing systems Nov 4, 2021 Issued
Array ( [id] => 17431702 [patent_doc_number] => 20220059411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH POROUS DIELECTRIC STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/517566 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517566 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517566
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH POROUS DIELECTRIC STRUCTURE Nov 1, 2021 Abandoned
Array ( [id] => 19812460 [patent_doc_number] => 12243873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Integrated circuit having three-dimensional transistors and seal ring structure with monitoring pattern [patent_app_type] => utility [patent_app_number] => 17/488830 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488830
Integrated circuit having three-dimensional transistors and seal ring structure with monitoring pattern Sep 28, 2021 Issued
Array ( [id] => 20113222 [patent_doc_number] => 12363977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Forming dielectric sidewall and bottom dielectric isolation in Fork-FET devices [patent_app_type] => utility [patent_app_number] => 17/463019 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 31 [patent_no_of_words] => 1145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463019
Forming dielectric sidewall and bottom dielectric isolation in Fork-FET devices Aug 30, 2021 Issued
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