
Tuan A. Hoang
Examiner (ID: 7516, Phone: (571)270-0406 , Office: P/2896 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2896, 2898 |
| Total Applications | 557 |
| Issued Applications | 368 |
| Pending Applications | 78 |
| Abandoned Applications | 131 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20245969
[patent_doc_number] => 12426314
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-23
[patent_title] => Strain generation and anchoring in gate-all-around field effect transistors
[patent_app_type] => utility
[patent_app_number] => 17/446479
[patent_app_country] => US
[patent_app_date] => 2021-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 7485
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446479
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/446479 | Strain generation and anchoring in gate-all-around field effect transistors | Aug 30, 2021 | Issued |
Array
(
[id] => 19928232
[patent_doc_number] => 12302543
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Integrated circuit device with reduced via resistance
[patent_app_type] => utility
[patent_app_number] => 17/461322
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 9711
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461322
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/461322 | Integrated circuit device with reduced via resistance | Aug 29, 2021 | Issued |
Array
(
[id] => 18227103
[patent_doc_number] => 20230066097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => ACTIVE REGION CUT PROCESS
[patent_app_type] => utility
[patent_app_number] => 17/461247
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8183
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461247
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/461247 | Active region cut process | Aug 29, 2021 | Issued |
Array
(
[id] => 18223311
[patent_doc_number] => 20230062305
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => Mandrel Structures and Methods of Fabricating the Same in Semiconductor Devices
[patent_app_type] => utility
[patent_app_number] => 17/460488
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7676
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460488
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460488 | Mandrel structures and methods of fabricating the same in semiconductor devices | Aug 29, 2021 | Issued |
Array
(
[id] => 19858321
[patent_doc_number] => 12261172
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-25
[patent_title] => Semiconductor devices and methods of manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 17/460198
[patent_app_country] => US
[patent_app_date] => 2021-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5983
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460198
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460198 | Semiconductor devices and methods of manufacturing thereof | Aug 27, 2021 | Issued |
Array
(
[id] => 18224045
[patent_doc_number] => 20230063039
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/459784
[patent_app_country] => US
[patent_app_date] => 2021-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9917
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459784
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/459784 | Semiconductor devices and methods of manufacturing thereof | Aug 26, 2021 | Issued |
Array
(
[id] => 17295608
[patent_doc_number] => 20210391447
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => Inner Spacer Formation in Multi-Gate Transistors
[patent_app_type] => utility
[patent_app_number] => 17/458087
[patent_app_country] => US
[patent_app_date] => 2021-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11166
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458087
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/458087 | Inner spacer formation in multi-gate transistors | Aug 25, 2021 | Issued |
Array
(
[id] => 19912569
[patent_doc_number] => 12288788
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-29
[patent_title] => Integrated circuit devices
[patent_app_type] => utility
[patent_app_number] => 17/410326
[patent_app_country] => US
[patent_app_date] => 2021-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 36
[patent_no_of_words] => 5766
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410326
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/410326 | Integrated circuit devices | Aug 23, 2021 | Issued |
Array
(
[id] => 17277903
[patent_doc_number] => 20210384101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-09
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/408988
[patent_app_country] => US
[patent_app_date] => 2021-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6616
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408988
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/408988 | Semiconductor package | Aug 22, 2021 | Issued |
Array
(
[id] => 19875105
[patent_doc_number] => 12267991
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-01
[patent_title] => Multi-gate field-effect transistors in integrated circuits
[patent_app_type] => utility
[patent_app_number] => 17/399748
[patent_app_country] => US
[patent_app_date] => 2021-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 30
[patent_no_of_words] => 12376
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399748
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/399748 | Multi-gate field-effect transistors in integrated circuits | Aug 10, 2021 | Issued |
Array
(
[id] => 19639710
[patent_doc_number] => 12170327
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-17
[patent_title] => Semiconductor structure and manufacturing method of the same
[patent_app_type] => utility
[patent_app_number] => 17/398668
[patent_app_country] => US
[patent_app_date] => 2021-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6567
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398668
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/398668 | Semiconductor structure and manufacturing method of the same | Aug 9, 2021 | Issued |
Array
(
[id] => 18180911
[patent_doc_number] => 20230041640
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/395879
[patent_app_country] => US
[patent_app_date] => 2021-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7010
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395879
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/395879 | Semiconductor structure and method for forming the same | Aug 5, 2021 | Issued |
Array
(
[id] => 19886956
[patent_doc_number] => 12272689
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-08
[patent_title] => Semiconductor structure with composite oxide layer
[patent_app_type] => utility
[patent_app_number] => 17/389685
[patent_app_country] => US
[patent_app_date] => 2021-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4715
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389685
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/389685 | Semiconductor structure with composite oxide layer | Jul 29, 2021 | Issued |
Array
(
[id] => 18040214
[patent_doc_number] => 20220384431
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/388005
[patent_app_country] => US
[patent_app_date] => 2021-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5328
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388005
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/388005 | Semiconductor device and method of forming the same | Jul 28, 2021 | Issued |
Array
(
[id] => 18148945
[patent_doc_number] => 20230022802
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-26
[patent_title] => BURIED POWER RAIL CONTACT
[patent_app_type] => utility
[patent_app_number] => 17/384908
[patent_app_country] => US
[patent_app_date] => 2021-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6629
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384908
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/384908 | Buried power rail contact | Jul 25, 2021 | Issued |
Array
(
[id] => 18160669
[patent_doc_number] => 20230027261
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-26
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/382859
[patent_app_country] => US
[patent_app_date] => 2021-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5848
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382859
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/382859 | Semiconductor devices and methods of manufacturing thereof | Jul 21, 2021 | Issued |
Array
(
[id] => 19094069
[patent_doc_number] => 11955536
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-09
[patent_title] => Semiconductor transistor structure and fabrication method thereof
[patent_app_type] => utility
[patent_app_number] => 17/377319
[patent_app_country] => US
[patent_app_date] => 2021-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3279
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377319
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/377319 | Semiconductor transistor structure and fabrication method thereof | Jul 14, 2021 | Issued |
Array
(
[id] => 17359947
[patent_doc_number] => 20220020743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-20
[patent_title] => SELF-ALIGNED ISOLATION FOR SELF-ALIGNED CONTACTS FOR VERTICAL FETS
[patent_app_type] => utility
[patent_app_number] => 17/373627
[patent_app_country] => US
[patent_app_date] => 2021-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9154
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373627
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/373627 | Self-aligned isolation for self-aligned contacts for vertical FETS | Jul 11, 2021 | Issued |
Array
(
[id] => 18125601
[patent_doc_number] => 20230011218
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-12
[patent_title] => FINFET WITH BOWL-SHAPED GATE ISOLATION AND METHOD
[patent_app_type] => utility
[patent_app_number] => 17/370330
[patent_app_country] => US
[patent_app_date] => 2021-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7132
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370330
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/370330 | FinFET with bowl-shaped gate isolation and method | Jul 7, 2021 | Issued |
Array
(
[id] => 18639638
[patent_doc_number] => 11764264
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-19
[patent_title] => LDD-free semiconductor structure and manufacturing method of the same
[patent_app_type] => utility
[patent_app_number] => 17/364426
[patent_app_country] => US
[patent_app_date] => 2021-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6044
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364426
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/364426 | LDD-free semiconductor structure and manufacturing method of the same | Jun 29, 2021 | Issued |