Search

Tuan H. Nguyen

Examiner (ID: 11261)

Most Active Art Unit
2813
Art Unit(s)
2813, 1104, 3992, 3991
Total Applications
1968
Issued Applications
1723
Pending Applications
53
Abandoned Applications
192

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5743232 [patent_doc_number] => 20060088957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/236866 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5769 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20060088957.pdf [firstpage_image] =>[orig_patent_app_number] => 11236866 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/236866
Method for manufacturing a semiconductor device Sep 27, 2005 Issued
Array ( [id] => 467366 [patent_doc_number] => 07235480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry' [patent_app_type] => utility [patent_app_number] => 11/236115 [patent_app_country] => US [patent_app_date] => 2005-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1752 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/235/07235480.pdf [firstpage_image] =>[orig_patent_app_number] => 11236115 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/236115
Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry Sep 25, 2005 Issued
Array ( [id] => 349161 [patent_doc_number] => 07495279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Embedded flash memory devices on SOI substrates and methods of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 11/223235 [patent_app_country] => US [patent_app_date] => 2005-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9631 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495279.pdf [firstpage_image] =>[orig_patent_app_number] => 11223235 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/223235
Embedded flash memory devices on SOI substrates and methods of manufacture thereof Sep 8, 2005 Issued
Array ( [id] => 840379 [patent_doc_number] => 07390707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Semiconductor device fabrication method' [patent_app_type] => utility [patent_app_number] => 11/220865 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 68 [patent_no_of_words] => 13804 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/390/07390707.pdf [firstpage_image] =>[orig_patent_app_number] => 11220865 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/220865
Semiconductor device fabrication method Sep 7, 2005 Issued
Array ( [id] => 806611 [patent_doc_number] => 07419843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'Method of manufacturing semiconductor probe having resistive tip' [patent_app_type] => utility [patent_app_number] => 11/212605 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3084 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/419/07419843.pdf [firstpage_image] =>[orig_patent_app_number] => 11212605 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212605
Method of manufacturing semiconductor probe having resistive tip Aug 28, 2005 Issued
Array ( [id] => 435859 [patent_doc_number] => 07262115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Method and apparatus for breaking semiconductor wafers' [patent_app_type] => utility [patent_app_number] => 11/213015 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6432 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/262/07262115.pdf [firstpage_image] =>[orig_patent_app_number] => 11213015 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213015
Method and apparatus for breaking semiconductor wafers Aug 25, 2005 Issued
Array ( [id] => 5796423 [patent_doc_number] => 20060033100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Anisotropically conductive connector and production process thereof, and probe member' [patent_app_type] => utility [patent_app_number] => 11/205174 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 23409 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20060033100.pdf [firstpage_image] =>[orig_patent_app_number] => 11205174 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/205174
Anisotropically conductive connector and production process thereof, and probe member Aug 16, 2005 Issued
Array ( [id] => 348717 [patent_doc_number] => 07494831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Process for making stacks of islands made of one semiconducting material encapsulated in another semiconducting material' [patent_app_type] => utility [patent_app_number] => 11/202316 [patent_app_country] => US [patent_app_date] => 2005-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2426 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/494/07494831.pdf [firstpage_image] =>[orig_patent_app_number] => 11202316 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/202316
Process for making stacks of islands made of one semiconducting material encapsulated in another semiconducting material Aug 11, 2005 Issued
Array ( [id] => 800333 [patent_doc_number] => 07425475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'Method for fabricating semiconductor device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/199166 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 12140 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/425/07425475.pdf [firstpage_image] =>[orig_patent_app_number] => 11199166 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199166
Method for fabricating semiconductor device and semiconductor device Aug 8, 2005 Issued
Array ( [id] => 435853 [patent_doc_number] => 07262109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor' [patent_app_type] => utility [patent_app_number] => 11/196087 [patent_app_country] => US [patent_app_date] => 2005-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4605 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/262/07262109.pdf [firstpage_image] =>[orig_patent_app_number] => 11196087 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196087
Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor Aug 2, 2005 Issued
Array ( [id] => 5239714 [patent_doc_number] => 20070018205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'STRUCTURE AND METHOD FOR IMPROVED STRESS AND YIELD IN pFETS WITH EMBEDDED SiGe SOURCE/DRAIN REGIONS' [patent_app_type] => utility [patent_app_number] => 11/161066 [patent_app_country] => US [patent_app_date] => 2005-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018205.pdf [firstpage_image] =>[orig_patent_app_number] => 11161066 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/161066
Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions Jul 20, 2005 Issued
Array ( [id] => 425045 [patent_doc_number] => 07271027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Castellation wafer level packaging of integrated circuit chips' [patent_app_type] => utility [patent_app_number] => 11/182427 [patent_app_country] => US [patent_app_date] => 2005-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 44 [patent_no_of_words] => 8686 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/271/07271027.pdf [firstpage_image] =>[orig_patent_app_number] => 11182427 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/182427
Castellation wafer level packaging of integrated circuit chips Jul 13, 2005 Issued
Array ( [id] => 568055 [patent_doc_number] => 07462527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Method of forming nitride films with high compressive stress for improved PFET device performance' [patent_app_type] => utility [patent_app_number] => 11/160705 [patent_app_country] => US [patent_app_date] => 2005-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1820 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/462/07462527.pdf [firstpage_image] =>[orig_patent_app_number] => 11160705 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/160705
Method of forming nitride films with high compressive stress for improved PFET device performance Jul 5, 2005 Issued
Array ( [id] => 5141959 [patent_doc_number] => 20070004175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Semiconductor wafer cutting blade and method' [patent_app_type] => utility [patent_app_number] => 11/172975 [patent_app_country] => US [patent_app_date] => 2005-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2669 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004175.pdf [firstpage_image] =>[orig_patent_app_number] => 11172975 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/172975
Semiconductor wafer cutting blade and method Jun 30, 2005 Issued
Array ( [id] => 415192 [patent_doc_number] => 07279375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Block contact architectures for nanoscale channel transistors' [patent_app_type] => utility [patent_app_number] => 11/173866 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 8368 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/279/07279375.pdf [firstpage_image] =>[orig_patent_app_number] => 11173866 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/173866
Block contact architectures for nanoscale channel transistors Jun 29, 2005 Issued
Array ( [id] => 891970 [patent_doc_number] => 07344962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Method of manufacturing dual orientation wafers' [patent_app_type] => utility [patent_app_number] => 11/160365 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 3846 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/344/07344962.pdf [firstpage_image] =>[orig_patent_app_number] => 11160365 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/160365
Method of manufacturing dual orientation wafers Jun 20, 2005 Issued
Array ( [id] => 830473 [patent_doc_number] => 07400028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-15 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/154745 [patent_app_country] => US [patent_app_date] => 2005-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 38 [patent_no_of_words] => 9514 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/400/07400028.pdf [firstpage_image] =>[orig_patent_app_number] => 11154745 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/154745
Semiconductor device Jun 16, 2005 Issued
Array ( [id] => 810493 [patent_doc_number] => 07417250 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-26 [patent_title] => 'Strained-silicon device with different silicon thicknesses' [patent_app_type] => utility [patent_app_number] => 11/151550 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3558 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/417/07417250.pdf [firstpage_image] =>[orig_patent_app_number] => 11151550 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/151550
Strained-silicon device with different silicon thicknesses Jun 13, 2005 Issued
Array ( [id] => 5894985 [patent_doc_number] => 20060003524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Method for forming trench memory cell structures for DRAMS' [patent_app_type] => utility [patent_app_number] => 11/152326 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003524.pdf [firstpage_image] =>[orig_patent_app_number] => 11152326 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152326
Method for forming trench memory cell structures for DRAMS Jun 13, 2005 Issued
Array ( [id] => 5642813 [patent_doc_number] => 20060281268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Short channel semiconductor device fabrication' [patent_app_type] => utility [patent_app_number] => 11/152596 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6957 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20060281268.pdf [firstpage_image] =>[orig_patent_app_number] => 11152596 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152596
Short channel semiconductor device fabrication Jun 13, 2005 Issued
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