
Tuan H. Nguyen
Examiner (ID: 11261)
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813, 1104, 3992, 3991 |
| Total Applications | 1968 |
| Issued Applications | 1723 |
| Pending Applications | 53 |
| Abandoned Applications | 192 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5743232
[patent_doc_number] => 20060088957
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-27
[patent_title] => 'Method for manufacturing a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/236866
[patent_app_country] => US
[patent_app_date] => 2005-09-28
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[pdf_file] => publications/A1/0088/20060088957.pdf
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Array
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[patent_doc_number] => 07235480
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[patent_kind] => B2
[patent_issue_date] => 2007-06-26
[patent_title] => 'Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry'
[patent_app_type] => utility
[patent_app_number] => 11/236115
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/236115 | Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry | Sep 25, 2005 | Issued |
Array
(
[id] => 349161
[patent_doc_number] => 07495279
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[patent_kind] => B2
[patent_issue_date] => 2009-02-24
[patent_title] => 'Embedded flash memory devices on SOI substrates and methods of manufacture thereof'
[patent_app_type] => utility
[patent_app_number] => 11/223235
[patent_app_country] => US
[patent_app_date] => 2005-09-09
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[patent_drawing_sheets_cnt] => 6
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/223235 | Embedded flash memory devices on SOI substrates and methods of manufacture thereof | Sep 8, 2005 | Issued |
Array
(
[id] => 840379
[patent_doc_number] => 07390707
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[patent_kind] => B2
[patent_issue_date] => 2008-06-24
[patent_title] => 'Semiconductor device fabrication method'
[patent_app_type] => utility
[patent_app_number] => 11/220865
[patent_app_country] => US
[patent_app_date] => 2005-09-08
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/220865 | Semiconductor device fabrication method | Sep 7, 2005 | Issued |
Array
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[patent_doc_number] => 07419843
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[patent_issue_date] => 2008-09-02
[patent_title] => 'Method of manufacturing semiconductor probe having resistive tip'
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[patent_app_number] => 11/212605
[patent_app_country] => US
[patent_app_date] => 2005-08-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/212605 | Method of manufacturing semiconductor probe having resistive tip | Aug 28, 2005 | Issued |
Array
(
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[patent_issue_date] => 2007-08-28
[patent_title] => 'Method and apparatus for breaking semiconductor wafers'
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[patent_app_number] => 11/213015
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/213015 | Method and apparatus for breaking semiconductor wafers | Aug 25, 2005 | Issued |
Array
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[patent_title] => 'Anisotropically conductive connector and production process thereof, and probe member'
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Array
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[id] => 348717
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[patent_issue_date] => 2009-02-24
[patent_title] => 'Process for making stacks of islands made of one semiconducting material encapsulated in another semiconducting material'
[patent_app_type] => utility
[patent_app_number] => 11/202316
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/202316 | Process for making stacks of islands made of one semiconducting material encapsulated in another semiconducting material | Aug 11, 2005 | Issued |
Array
(
[id] => 800333
[patent_doc_number] => 07425475
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[patent_issue_date] => 2008-09-16
[patent_title] => 'Method for fabricating semiconductor device and semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/199166 | Method for fabricating semiconductor device and semiconductor device | Aug 8, 2005 | Issued |
Array
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[id] => 435853
[patent_doc_number] => 07262109
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[patent_issue_date] => 2007-08-28
[patent_title] => 'Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor'
[patent_app_type] => utility
[patent_app_number] => 11/196087
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/196087 | Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor | Aug 2, 2005 | Issued |
Array
(
[id] => 5239714
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[patent_title] => 'STRUCTURE AND METHOD FOR IMPROVED STRESS AND YIELD IN pFETS WITH EMBEDDED SiGe SOURCE/DRAIN REGIONS'
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Array
(
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[patent_title] => 'Castellation wafer level packaging of integrated circuit chips'
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Array
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[patent_title] => 'Method of forming nitride films with high compressive stress for improved PFET device performance'
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Array
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Array
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Array
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Array
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