
Tuan Pham
Examiner (ID: 14490, Phone: (571)272-8097 , Office: P/2649 )
| Most Active Art Unit | 2649 |
| Art Unit(s) | 2649, 2618, 2647, 2643 |
| Total Applications | 1757 |
| Issued Applications | 1443 |
| Pending Applications | 70 |
| Abandoned Applications | 275 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2699177
[patent_doc_number] => 04996452
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-02-26
[patent_title] => 'ECL/TTL tristate buffer'
[patent_app_type] => 1
[patent_app_number] => 7/436846
[patent_app_country] => US
[patent_app_date] => 1989-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2469
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/996/04996452.pdf
[firstpage_image] =>[orig_patent_app_number] => 436846
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/436846 | ECL/TTL tristate buffer | Nov 14, 1989 | Issued |
Array
(
[id] => 2753836
[patent_doc_number] => 05021690
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-04
[patent_title] => 'Programmable logic array apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/434797
[patent_app_country] => US
[patent_app_date] => 1989-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 12599
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/021/05021690.pdf
[firstpage_image] =>[orig_patent_app_number] => 434797
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/434797 | Programmable logic array apparatus | Nov 12, 1989 | Issued |
Array
(
[id] => 2753726
[patent_doc_number] => 05021684
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-04
[patent_title] => 'Process, supply, temperature compensating CMOS output buffer'
[patent_app_type] => 1
[patent_app_number] => 7/434021
[patent_app_country] => US
[patent_app_date] => 1989-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3554
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 285
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/021/05021684.pdf
[firstpage_image] =>[orig_patent_app_number] => 434021
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/434021 | Process, supply, temperature compensating CMOS output buffer | Nov 8, 1989 | Issued |
Array
(
[id] => 2672956
[patent_doc_number] => 04999517
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-03-12
[patent_title] => 'Inverter circuit'
[patent_app_type] => 1
[patent_app_number] => 7/433472
[patent_app_country] => US
[patent_app_date] => 1989-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2633
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/999/04999517.pdf
[firstpage_image] =>[orig_patent_app_number] => 433472
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/433472 | Inverter circuit | Nov 7, 1989 | Issued |
Array
(
[id] => 2750606
[patent_doc_number] => 05015871
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-14
[patent_title] => 'Multiple external asynchronous triggers circuit'
[patent_app_type] => 1
[patent_app_number] => 7/431305
[patent_app_country] => US
[patent_app_date] => 1989-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1480
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/015/05015871.pdf
[firstpage_image] =>[orig_patent_app_number] => 431305
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/431305 | Multiple external asynchronous triggers circuit | Nov 2, 1989 | Issued |
Array
(
[id] => 2854047
[patent_doc_number] => 05105103
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-14
[patent_title] => 'Integrated binary amplifier having a Darlington configuration'
[patent_app_type] => 1
[patent_app_number] => 7/430668
[patent_app_country] => US
[patent_app_date] => 1989-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4736
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 22
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/105/05105103.pdf
[firstpage_image] =>[orig_patent_app_number] => 430668
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/430668 | Integrated binary amplifier having a Darlington configuration | Nov 1, 1989 | Issued |
Array
(
[id] => 2710987
[patent_doc_number] => 05013938
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-07
[patent_title] => 'ECL cutoff driver circuit with reduced stanby power dissipation'
[patent_app_type] => 1
[patent_app_number] => 7/430431
[patent_app_country] => US
[patent_app_date] => 1989-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3707
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/013/05013938.pdf
[firstpage_image] =>[orig_patent_app_number] => 430431
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/430431 | ECL cutoff driver circuit with reduced stanby power dissipation | Oct 31, 1989 | Issued |
Array
(
[id] => 2711045
[patent_doc_number] => 05013941
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-07
[patent_title] => 'TTL to ECL/CML translator circuit'
[patent_app_type] => 1
[patent_app_number] => 7/395259
[patent_app_country] => US
[patent_app_date] => 1989-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 6216
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/013/05013941.pdf
[firstpage_image] =>[orig_patent_app_number] => 395259
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/395259 | TTL to ECL/CML translator circuit | Aug 16, 1989 | Issued |
Array
(
[id] => 2699196
[patent_doc_number] => 04996453
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-02-26
[patent_title] => 'Power down circuit for low-power circuit with dual supply voltages'
[patent_app_type] => 1
[patent_app_number] => 7/387546
[patent_app_country] => US
[patent_app_date] => 1989-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 7809
[patent_no_of_claims] => 21
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/996/04996453.pdf
[firstpage_image] =>[orig_patent_app_number] => 387546
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/387546 | Power down circuit for low-power circuit with dual supply voltages | Jul 27, 1989 | Issued |