
Tuan Pham
Examiner (ID: 14490, Phone: (571)272-8097 , Office: P/2649 )
| Most Active Art Unit | 2649 |
| Art Unit(s) | 2649, 2618, 2647, 2643 |
| Total Applications | 1757 |
| Issued Applications | 1443 |
| Pending Applications | 70 |
| Abandoned Applications | 275 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2852253
[patent_doc_number] => 05172400
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-15
[patent_title] => 'Frequency divider employing multiple stages of master/slave flip-flops'
[patent_app_type] => 1
[patent_app_number] => 7/680240
[patent_app_country] => US
[patent_app_date] => 1991-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 5345
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/172/05172400.pdf
[firstpage_image] =>[orig_patent_app_number] => 680240
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/680240 | Frequency divider employing multiple stages of master/slave flip-flops | Apr 2, 1991 | Issued |
Array
(
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[patent_doc_number] => 05187724
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[patent_kind] => NA
[patent_issue_date] => 1993-02-16
[patent_title] => 'Absolute position detecting device'
[patent_app_type] => 1
[patent_app_number] => 7/679479
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[patent_app_date] => 1991-04-02
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[firstpage_image] =>[orig_patent_app_number] => 679479
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/679479 | Absolute position detecting device | Apr 1, 1991 | Issued |
Array
(
[id] => 2862856
[patent_doc_number] => 05134638
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-28
[patent_title] => 'Shift register connection between electrical circuits'
[patent_app_type] => 1
[patent_app_number] => 7/678458
[patent_app_country] => US
[patent_app_date] => 1991-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[firstpage_image] =>[orig_patent_app_number] => 678458
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/678458 | Shift register connection between electrical circuits | Mar 31, 1991 | Issued |
Array
(
[id] => 2865070
[patent_doc_number] => 05127036
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[patent_kind] => NA
[patent_issue_date] => 1992-06-30
[patent_title] => 'Fifty percent duty cycle divided-by-m counter'
[patent_app_type] => 1
[patent_app_number] => 7/677913
[patent_app_country] => US
[patent_app_date] => 1991-04-01
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 5765
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[pdf_file] => patents/05/127/05127036.pdf
[firstpage_image] =>[orig_patent_app_number] => 677913
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/677913 | Fifty percent duty cycle divided-by-m counter | Mar 31, 1991 | Issued |
Array
(
[id] => 2841405
[patent_doc_number] => 05175753
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[patent_kind] => NA
[patent_issue_date] => 1992-12-29
[patent_title] => 'Counter cell including a latch circuit, control circuit and a pull-up circuit'
[patent_app_type] => 1
[patent_app_number] => 7/678510
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[pdf_file] => patents/05/175/05175753.pdf
[firstpage_image] =>[orig_patent_app_number] => 678510
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/678510 | Counter cell including a latch circuit, control circuit and a pull-up circuit | Mar 31, 1991 | Issued |
Array
(
[id] => 2990329
[patent_doc_number] => 05204884
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-20
[patent_title] => 'System for high-speed measurement and sorting of particles'
[patent_app_type] => 1
[patent_app_number] => 7/671009
[patent_app_country] => US
[patent_app_date] => 1991-03-18
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[pdf_file] => patents/05/204/05204884.pdf
[firstpage_image] =>[orig_patent_app_number] => 671009
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/671009 | System for high-speed measurement and sorting of particles | Mar 17, 1991 | Issued |
Array
(
[id] => 2904621
[patent_doc_number] => 05270979
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-14
[patent_title] => 'Method for optimum erasing of EEPROM'
[patent_app_type] => 1
[patent_app_number] => 7/670246
[patent_app_country] => US
[patent_app_date] => 1991-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 11506
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[pdf_file] => patents/05/270/05270979.pdf
[firstpage_image] =>[orig_patent_app_number] => 670246
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/670246 | Method for optimum erasing of EEPROM | Mar 14, 1991 | Issued |
| 07/646795 | ON-CHIP INTERMEDIATE DRIVER FOR DISCRETE WSI SYSTEMS | Mar 10, 1991 | Abandoned |
Array
(
[id] => 2985811
[patent_doc_number] => 05257149
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-26
[patent_title] => 'Disc drive with offset address field'
[patent_app_type] => 1
[patent_app_number] => 7/654900
[patent_app_country] => US
[patent_app_date] => 1991-02-13
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/257/05257149.pdf
[firstpage_image] =>[orig_patent_app_number] => 654900
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/654900 | Disc drive with offset address field | Feb 12, 1991 | Issued |
Array
(
[id] => 2913276
[patent_doc_number] => 05249158
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-28
[patent_title] => 'Flash memory blocking architecture'
[patent_app_type] => 1
[patent_app_number] => 7/654263
[patent_app_country] => US
[patent_app_date] => 1991-02-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/249/05249158.pdf
[firstpage_image] =>[orig_patent_app_number] => 654263
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/654263 | Flash memory blocking architecture | Feb 10, 1991 | Issued |
Array
(
[id] => 2978614
[patent_doc_number] => 05182472
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-26
[patent_title] => 'Logic circuit with bipolar CMOS configuration'
[patent_app_type] => 1
[patent_app_number] => 7/651802
[patent_app_country] => US
[patent_app_date] => 1991-02-07
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/182/05182472.pdf
[firstpage_image] =>[orig_patent_app_number] => 651802
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/651802 | Logic circuit with bipolar CMOS configuration | Feb 6, 1991 | Issued |
Array
(
[id] => 2739664
[patent_doc_number] => 05077490
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-31
[patent_title] => 'Schottky-diode emulator for BiCMOS logic circuit'
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[pdf_file] => patents/05/077/05077490.pdf
[firstpage_image] =>[orig_patent_app_number] => 647794
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/647794 | Schottky-diode emulator for BiCMOS logic circuit | Jan 29, 1991 | Issued |
Array
(
[id] => 2818457
[patent_doc_number] => 05122692
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-16
[patent_title] => 'High speed level conversion circuit including a switch circuit'
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[pdf_file] => patents/05/122/05122692.pdf
[firstpage_image] =>[orig_patent_app_number] => 645445
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/645445 | High speed level conversion circuit including a switch circuit | Jan 23, 1991 | Issued |
Array
(
[id] => 2777823
[patent_doc_number] => 05075578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-24
[patent_title] => 'Input buffer regenerative latch'
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[firstpage_image] =>[orig_patent_app_number] => 641983
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/641983 | Input buffer regenerative latch | Jan 15, 1991 | Issued |
Array
(
[id] => 2793103
[patent_doc_number] => 05101124
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[patent_kind] => NA
[patent_issue_date] => 1992-03-31
[patent_title] => 'ECL to TTL translator circuit with improved slew rate'
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[pdf_file] => patents/05/101/05101124.pdf
[firstpage_image] =>[orig_patent_app_number] => 639793
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/639793 | ECL to TTL translator circuit with improved slew rate | Jan 9, 1991 | Issued |
Array
(
[id] => 2684977
[patent_doc_number] => 05066876
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-19
[patent_title] => 'Circuit for converting ECL level signals to MOS level signals'
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[pdf_file] => patents/05/066/05066876.pdf
[firstpage_image] =>[orig_patent_app_number] => 632167
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/632167 | Circuit for converting ECL level signals to MOS level signals | Dec 20, 1990 | Issued |
Array
(
[id] => 2788831
[patent_doc_number] => 05142168
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-25
[patent_title] => 'Emitter-coupled logic balanced signal transmission circuit'
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[pdf_file] => patents/05/142/05142168.pdf
[firstpage_image] =>[orig_patent_app_number] => 630061
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/630061 | Emitter-coupled logic balanced signal transmission circuit | Dec 18, 1990 | Issued |
Array
(
[id] => 2863627
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[patent_issue_date] => 1992-11-24
[patent_title] => 'High speed output circuit without fluctuation for semiconductor integrated circuits'
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[pdf_file] => patents/05/166/05166551.pdf
[firstpage_image] =>[orig_patent_app_number] => 628906
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/628906 | High speed output circuit without fluctuation for semiconductor integrated circuits | Dec 17, 1990 | Issued |
Array
(
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[patent_doc_number] => 05065049
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[patent_issue_date] => 1991-11-12
[patent_title] => 'MOS driver circuit having clamp means to hold the output voltage constant regardless of variations in the operating voltage'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/621829 | MOS driver circuit having clamp means to hold the output voltage constant regardless of variations in the operating voltage | Dec 3, 1990 | Issued |
Array
(
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[patent_doc_number] => 05130564
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[patent_kind] => NA
[patent_issue_date] => 1992-07-14
[patent_title] => 'Signal delay circuit for minimizing the delay time dependence on power supply voltage variation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/620720 | Signal delay circuit for minimizing the delay time dependence on power supply voltage variation | Dec 2, 1990 | Issued |