Search

Tuan T. Nguyen

Examiner (ID: 11337)

Most Active Art Unit
2824
Art Unit(s)
2824, 2818
Total Applications
1795
Issued Applications
1747
Pending Applications
26
Abandoned Applications
27

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10377679 [patent_doc_number] => 20150262686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'ERASE SYSTEM AND METHOD OF NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/723525 [patent_app_country] => US [patent_app_date] => 2015-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 31346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723525 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723525
Erase system and method of nonvolatile memory device May 27, 2015 Issued
Array ( [id] => 11431857 [patent_doc_number] => 09570178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Semiconductor memory device and operating method thereof' [patent_app_type] => utility [patent_app_number] => 14/723168 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6545 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723168 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723168
Semiconductor memory device and operating method thereof May 26, 2015 Issued
Array ( [id] => 10463624 [patent_doc_number] => 20150348639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'CELL STRING AND READING METHOD FOR THE CELL STRING' [patent_app_type] => utility [patent_app_number] => 14/722605 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6428 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14722605 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/722605
Cell string and reading method for the cell string May 26, 2015 Issued
Array ( [id] => 11770097 [patent_doc_number] => 09378782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-28 [patent_title] => 'Apparatus with write-back buffer and associated methods' [patent_app_type] => utility [patent_app_number] => 14/720811 [patent_app_country] => US [patent_app_date] => 2015-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6249 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14720811 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/720811
Apparatus with write-back buffer and associated methods May 23, 2015 Issued
Array ( [id] => 11293516 [patent_doc_number] => 20160343448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'SYSTEM AND METHOD FOR MEMORY INTEGRATED CIRCUIT CHIP WRITE ABORT INDICATION' [patent_app_type] => utility [patent_app_number] => 14/718488 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8087 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14718488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/718488
System and method for memory integrated circuit chip write abort indication May 20, 2015 Issued
Array ( [id] => 10617413 [patent_doc_number] => 09336860 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-10 [patent_title] => 'Complementary bipolar SRAM' [patent_app_type] => utility [patent_app_number] => 14/717218 [patent_app_country] => US [patent_app_date] => 2015-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6835 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14717218 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/717218
Complementary bipolar SRAM May 19, 2015 Issued
Array ( [id] => 10343353 [patent_doc_number] => 20150228359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'FAILURE DIAGNOSIS CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/695110 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4021 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14695110 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/695110
Failure diagnosis circuit Apr 23, 2015 Issued
Array ( [id] => 10336645 [patent_doc_number] => 20150221650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor' [patent_app_type] => utility [patent_app_number] => 14/688122 [patent_app_country] => US [patent_app_date] => 2015-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 18213 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14688122 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/688122
Method of maintaining the state of semiconductor memory having electrically floating body transistor Apr 15, 2015 Issued
Array ( [id] => 10551119 [patent_doc_number] => 09275750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Reduction of read disturb errors' [patent_app_type] => utility [patent_app_number] => 14/684429 [patent_app_country] => US [patent_app_date] => 2015-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 13709 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14684429 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/684429
Reduction of read disturb errors Apr 11, 2015 Issued
Array ( [id] => 11103638 [patent_doc_number] => 20160300608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'HYBRID ANALOG AND DIGITAL MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/683850 [patent_app_country] => US [patent_app_date] => 2015-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14683850 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/683850
Hybrid analog and digital memory device Apr 9, 2015 Issued
Array ( [id] => 10329069 [patent_doc_number] => 20150214073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'REDUCED-NOISE REFERENCE VOLTAGE PLATFORM FOR A VOLTAGE CONVERTER DEVICE' [patent_app_type] => utility [patent_app_number] => 14/683556 [patent_app_country] => US [patent_app_date] => 2015-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8330 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14683556 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/683556
Reduced-noise reference voltage platform for a voltage converter device Apr 9, 2015 Issued
Array ( [id] => 10425915 [patent_doc_number] => 20150310926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING FUSE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/682967 [patent_app_country] => US [patent_app_date] => 2015-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14682967 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/682967
Semiconductor device including fuse circuit Apr 8, 2015 Issued
Array ( [id] => 10165115 [patent_doc_number] => 09196342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Circuit and method for spin-torque MRAM bit line and source line voltage regulation' [patent_app_type] => utility [patent_app_number] => 14/676100 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676100 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676100
Circuit and method for spin-torque MRAM bit line and source line voltage regulation Mar 31, 2015 Issued
Array ( [id] => 10624517 [patent_doc_number] => 09343468 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-17 [patent_title] => 'Feed-forward bidirectional implanted split-gate flash memory cell' [patent_app_type] => utility [patent_app_number] => 14/669886 [patent_app_country] => US [patent_app_date] => 2015-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3614 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14669886 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/669886
Feed-forward bidirectional implanted split-gate flash memory cell Mar 25, 2015 Issued
Array ( [id] => 10597114 [patent_doc_number] => 09318209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-19 [patent_title] => 'Digitally controlled source side select gate offset in 3D NAND memory erase' [patent_app_type] => utility [patent_app_number] => 14/667014 [patent_app_country] => US [patent_app_date] => 2015-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 9616 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14667014 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/667014
Digitally controlled source side select gate offset in 3D NAND memory erase Mar 23, 2015 Issued
Array ( [id] => 10631276 [patent_doc_number] => 09349431 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-24 [patent_title] => 'Systems and methods to refresh storage elements' [patent_app_type] => utility [patent_app_number] => 14/660366 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 11561 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14660366 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/660366
Systems and methods to refresh storage elements Mar 16, 2015 Issued
Array ( [id] => 10402443 [patent_doc_number] => 20150287452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'DRAM SECURITY ERASE' [patent_app_type] => utility [patent_app_number] => 14/642588 [patent_app_country] => US [patent_app_date] => 2015-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6616 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14642588 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/642588
DRAM security erase Mar 8, 2015 Issued
Array ( [id] => 10302777 [patent_doc_number] => 20150187776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making' [patent_app_type] => utility [patent_app_number] => 14/637688 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 116 [patent_figures_cnt] => 116 [patent_no_of_words] => 31503 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14637688 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/637688
Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making Mar 3, 2015 Issued
Array ( [id] => 10285747 [patent_doc_number] => 20150170745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'FAST PROGRAMMING MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/632791 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14632791 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/632791
Fast programming memory device Feb 25, 2015 Issued
Array ( [id] => 11681115 [patent_doc_number] => 09679648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Memory cells, memory cell arrays, methods of using and methods of making' [patent_app_type] => utility [patent_app_number] => 14/630185 [patent_app_country] => US [patent_app_date] => 2015-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 50 [patent_no_of_words] => 26618 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14630185 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/630185
Memory cells, memory cell arrays, methods of using and methods of making Feb 23, 2015 Issued
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