Search

Tuan T. Nguyen

Examiner (ID: 8826)

Most Active Art Unit
2824
Art Unit(s)
2824, 2818
Total Applications
1795
Issued Applications
1748
Pending Applications
26
Abandoned Applications
27

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17908432 [patent_doc_number] => 11462292 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-04 [patent_title] => Error correction circuit of semiconductor memory device and semiconductor memory device including the same [patent_app_type] => utility [patent_app_number] => 17/227582 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 36 [patent_no_of_words] => 13033 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227582 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/227582
Error correction circuit of semiconductor memory device and semiconductor memory device including the same Apr 11, 2021 Issued
Array ( [id] => 18918975 [patent_doc_number] => 11881263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Method, system and device for integration of volatile and non-volatile memory bitcells [patent_app_type] => utility [patent_app_number] => 17/221670 [patent_app_country] => US [patent_app_date] => 2021-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 28703 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17221670 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/221670
Method, system and device for integration of volatile and non-volatile memory bitcells Apr 1, 2021 Issued
Array ( [id] => 17431472 [patent_doc_number] => 20220059181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => DETERMINATION OF STATE METRICS OF MEMORY SUB-SYSTEMS FOLLOWING POWER EVENTS [patent_app_type] => utility [patent_app_number] => 17/301348 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301348 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301348
Determination of state metrics of memory sub-systems following power events Mar 30, 2021 Issued
Array ( [id] => 17508838 [patent_doc_number] => 20220101941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => MEMORY CONTROLLERS HAVING SIMPLIFIED BISR LOGIC CIRCUIT, METHODS OF OPERATING THE MEMORY CONTROLLER, AND MEMORY SYSTEMS INCLUDING THE MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 17/203605 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17203605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/203605
Memory controllers having simplified BISR logic circuit, methods of operating the memory controller, and memory systems including the memory controller Mar 15, 2021 Issued
Array ( [id] => 18578746 [patent_doc_number] => 11735285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-22 [patent_title] => Detection of address bus corruption for data storage devices [patent_app_type] => utility [patent_app_number] => 17/200528 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8540 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200528 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200528
Detection of address bus corruption for data storage devices Mar 11, 2021 Issued
Array ( [id] => 17795339 [patent_doc_number] => 20220254431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => MEMORY CONTROL METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 17/195547 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195547 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/195547
Memory control method, memory storage device, and memory control circuit unit Mar 7, 2021 Issued
Array ( [id] => 17941505 [patent_doc_number] => 11475964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Method for programming a memory system [patent_app_type] => utility [patent_app_number] => 17/187672 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2638 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187672 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187672
Method for programming a memory system Feb 25, 2021 Issued
Array ( [id] => 18137104 [patent_doc_number] => 11562792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Memory system having a non-volatile memory and a controller configured to switch a mode for controlling an access operation to the non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/184991 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 42 [patent_no_of_words] => 19554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184991
Memory system having a non-volatile memory and a controller configured to switch a mode for controlling an access operation to the non-volatile memory Feb 24, 2021 Issued
Array ( [id] => 16904510 [patent_doc_number] => 20210183426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => Memory Cells and Arrays of Memory Cells [patent_app_type] => utility [patent_app_number] => 17/185488 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185488 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185488
Memory cells and arrays of memory cells Feb 24, 2021 Issued
Array ( [id] => 18190456 [patent_doc_number] => 11581057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/161260 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13036 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161260 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161260
Memory device and method of operating the same Jan 27, 2021 Issued
Array ( [id] => 17818381 [patent_doc_number] => 11424002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Memory system that includes a NAND flash memory and a memory controller [patent_app_type] => utility [patent_app_number] => 17/158161 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 18208 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158161
Memory system that includes a NAND flash memory and a memory controller Jan 25, 2021 Issued
Array ( [id] => 18031802 [patent_doc_number] => 11514997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Controller, a storage device including the controller, and a reading method of the storage device [patent_app_type] => utility [patent_app_number] => 17/156801 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 15274 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/156801
Controller, a storage device including the controller, and a reading method of the storage device Jan 24, 2021 Issued
Array ( [id] => 17787592 [patent_doc_number] => 11410726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Integrated circuit devices for driving conductors to target voltage levels [patent_app_type] => utility [patent_app_number] => 17/147653 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 10973 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147653
Integrated circuit devices for driving conductors to target voltage levels Jan 12, 2021 Issued
Array ( [id] => 17923445 [patent_doc_number] => 11466685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Driver circuit equipped with power gating circuit [patent_app_type] => utility [patent_app_number] => 17/138252 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5021 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138252
Driver circuit equipped with power gating circuit Dec 29, 2020 Issued
Array ( [id] => 18031761 [patent_doc_number] => 11514956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Sense amplifier sleep state for leakage savings without bias mismatch [patent_app_type] => utility [patent_app_number] => 17/133956 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2727 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133956
Sense amplifier sleep state for leakage savings without bias mismatch Dec 23, 2020 Issued
Array ( [id] => 17941510 [patent_doc_number] => 11475969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Scan optimization using data selection across wordline of a memory array [patent_app_type] => utility [patent_app_number] => 17/247633 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8250 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247633 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247633
Scan optimization using data selection across wordline of a memory array Dec 17, 2020 Issued
Array ( [id] => 17606937 [patent_doc_number] => 11335429 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-17 [patent_title] => Error recovery operations within a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/122864 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8891 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122864
Error recovery operations within a memory sub-system Dec 14, 2020 Issued
Array ( [id] => 16715382 [patent_doc_number] => 20210082529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => METHODS FOR DETECTING AND MITIGATING MEMORY MEDIA DEGRADATION AND MEMORY DEVICES EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 17/107235 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107235 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107235
Methods for detecting and mitigating memory media degradation and memory devices employing the same Nov 29, 2020 Issued
Array ( [id] => 17573946 [patent_doc_number] => 11322220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Memory system including a flash memory device and a memory controller [patent_app_type] => utility [patent_app_number] => 16/953485 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4820 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953485 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953485
Memory system including a flash memory device and a memory controller Nov 19, 2020 Issued
Array ( [id] => 17878353 [patent_doc_number] => 11450374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Memory controller for strobe-based memory systems [patent_app_type] => utility [patent_app_number] => 16/953196 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953196
Memory controller for strobe-based memory systems Nov 18, 2020 Issued
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