Tuan Thieu Lam

Array ( [id] => 17964538 [patent_doc_number] => 20220345119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => CONTROL OF BIAS CURRENT TO A LOAD [patent_app_type] => utility [patent_app_number] => 17/729844 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18318026 [patent_doc_number] => 11632119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-18 [patent_title] => Programmable fractional ripple divider [patent_app_type] => utility [patent_app_number] => 17/727922 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17727922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18983232 [patent_doc_number] => 11908417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Gate driving circuit and display device having the same [patent_app_type] => utility [patent_app_number] => 17/728584 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12172 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17764695 [patent_doc_number] => 20220238308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => DEVICE FOR FORMING PHYSICAL PLASMA ON A SURFACE OF AN OBJECT [patent_app_type] => utility [patent_app_number] => 17/723945 [patent_app_country] => US [patent_app_date] => 2022-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18697193 [patent_doc_number] => 20230327652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => SEMICONDUCTOR DEVICE AND INPUT SIGNAL CONTROLLING METHOD [patent_app_type] => utility [patent_app_number] => 17/717728 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17717728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19016902 [patent_doc_number] => 11923850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Parasitic pulse cancelation circuit [patent_app_type] => utility [patent_app_number] => 17/715223 [patent_app_country] => US [patent_app_date] => 2022-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4520 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17715223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17950217 [patent_doc_number] => 20220337236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => POWER SWITCHING CIRCUIT AND CORRESPONDING METHOD OF OPERATION [patent_app_type] => utility [patent_app_number] => 17/658016 [patent_app_country] => US [patent_app_date] => 2022-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19016908 [patent_doc_number] => 11923856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Low-latency time-to-digital converter with reduced quantization step [patent_app_type] => utility [patent_app_number] => 17/713901 [patent_app_country] => US [patent_app_date] => 2022-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7958 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18782754 [patent_doc_number] => 11824530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Low latency, broadband power-domain offset-correction signal level circuit implementation [patent_app_type] => utility [patent_app_number] => 17/712026 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17738854 [patent_doc_number] => 20220224316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => HIGH PERFORMANCE FAST MUX-D SCAN FLIP-FLOP [patent_app_type] => utility [patent_app_number] => 17/711638 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19796855 [patent_doc_number] => 12237836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Signal chatter mitigation [patent_app_type] => utility [patent_app_number] => 17/710533 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6963 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17986858 [patent_doc_number] => 20220352895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => MICROCONTROLLER, OPERATION SYSTEM AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/708689 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18593923 [patent_doc_number] => 11742838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Flip flop and design method for integrated circuit including the same [patent_app_type] => utility [patent_app_number] => 17/707044 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12962 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17708054 [patent_doc_number] => 20220208062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => GATE DRIVER AND DISPLAY PANEL HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/699040 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18579553 [patent_doc_number] => 11736097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Clock signal delay path unit and semiconductor memory device including the same [patent_app_type] => utility [patent_app_number] => 17/695168 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 12281 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17692502 [patent_doc_number] => 20220199795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => GALLIUM NITRIDE COMPONENT AND DRIVE CIRCUIT THEREOF [patent_app_type] => utility [patent_app_number] => 17/695539 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17870663 [patent_doc_number] => 20220293400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => PLASMA CHAMBER WITH ANCILLARY REACTION CHAMBER [patent_app_type] => utility [patent_app_number] => 17/654577 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18447453 [patent_doc_number] => 11683033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Apparatuses and methods for compensating for crosstalk noise at input receiver circuits [patent_app_type] => utility [patent_app_number] => 17/687959 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 13370 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18234244 [patent_doc_number] => 11598797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Duty timing detector for detecting duty timing of toggle signal, device including the duty timing detector, and method of operating toggle signal receiving device [patent_app_type] => utility [patent_app_number] => 17/682356 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17887435 [patent_doc_number] => 20220302913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => HIGH-SPEED DIGITAL SIGNAL DRIVER WITH LOW POWER CONSUMPTION [patent_app_type] => utility [patent_app_number] => 17/676994 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676994 [rel_patent_id] =>[rel_patent_doc_number] =>)