Search

Tuan V. Ho

Examiner (ID: 8114, Phone: (571)272-7365 , Office: P/2661 )

Most Active Art Unit
2661
Art Unit(s)
2613, 2615, 2602, 2712, 2612, 2606, 2661, 2622, 2604
Total Applications
2139
Issued Applications
1731
Pending Applications
101
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14366393 [patent_doc_number] => 10304508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Magnetoresistive element and memory circuit including a free layer [patent_app_type] => utility [patent_app_number] => 15/578377 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 46 [patent_no_of_words] => 14773 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15578377 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/578377
Magnetoresistive element and memory circuit including a free layer May 30, 2016 Issued
Array ( [id] => 11483077 [patent_doc_number] => 09589627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-07 [patent_title] => 'Methods and devices for a DDR memory driver using a voltage translation capacitor' [patent_app_type] => utility [patent_app_number] => 15/169508 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169508 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/169508
Methods and devices for a DDR memory driver using a voltage translation capacitor May 30, 2016 Issued
Array ( [id] => 12989350 [patent_doc_number] => 20170345509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => Sensing Amplifier Comprising A Built-In Sensing Offset For Flash Memory Devices [patent_app_type] => utility [patent_app_number] => 15/163548 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -42 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163548 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/163548
Sensing amplifier comprising a built-in sensing offset for flash memory devices May 23, 2016 Issued
Array ( [id] => 11551340 [patent_doc_number] => 09620194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-11 [patent_title] => 'Stacked memory device having serial to parallel address conversion, refresh control unit, and pipe control unit' [patent_app_type] => utility [patent_app_number] => 15/153383 [patent_app_country] => US [patent_app_date] => 2016-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15153383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/153383
Stacked memory device having serial to parallel address conversion, refresh control unit, and pipe control unit May 11, 2016 Issued
Array ( [id] => 11125120 [patent_doc_number] => 20160322094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'MEMORY DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/146994 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 16769 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15146994 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/146994
Memory device having wiring layout for electrically connecting to switch and capacitor components May 4, 2016 Issued
Array ( [id] => 11701556 [patent_doc_number] => 09691479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-27 [patent_title] => 'Method of operating and apparatus of memristor arrays with diagonal lines interconnect between memristor cells' [patent_app_type] => utility [patent_app_number] => 15/142995 [patent_app_country] => US [patent_app_date] => 2016-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 12056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15142995 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/142995
Method of operating and apparatus of memristor arrays with diagonal lines interconnect between memristor cells Apr 28, 2016 Issued
Array ( [id] => 11431806 [patent_doc_number] => 09570127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-14 [patent_title] => 'Semiconductor memory device with cut-off voltage and operating method thereof' [patent_app_type] => utility [patent_app_number] => 15/134615 [patent_app_country] => US [patent_app_date] => 2016-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134615 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/134615
Semiconductor memory device with cut-off voltage and operating method thereof Apr 20, 2016 Issued
Array ( [id] => 14800681 [patent_doc_number] => 10403348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Large current-readout ferroelectric single-crystal thin film memory as well as method of preparing the same and method of operating the same [patent_app_type] => utility [patent_app_number] => 15/556889 [patent_app_country] => US [patent_app_date] => 2016-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 13009 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15556889 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/556889
Large current-readout ferroelectric single-crystal thin film memory as well as method of preparing the same and method of operating the same Apr 11, 2016 Issued
Array ( [id] => 11431813 [patent_doc_number] => 09570134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-14 [patent_title] => 'Reducing transactional latency in address decoding' [patent_app_type] => utility [patent_app_number] => 15/087791 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15087791 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/087791
Reducing transactional latency in address decoding Mar 30, 2016 Issued
Array ( [id] => 11659876 [patent_doc_number] => 09672887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Semiconductor memory capable of reading data without accessing memory cell' [patent_app_type] => utility [patent_app_number] => 15/066851 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15066851 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/066851
Semiconductor memory capable of reading data without accessing memory cell Mar 9, 2016 Issued
Array ( [id] => 11959172 [patent_doc_number] => 20170263324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'SECTOR RETIREMENT FOR SPLIT-GATE MEMORY' [patent_app_type] => utility [patent_app_number] => 15/064813 [patent_app_country] => US [patent_app_date] => 2016-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15064813 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/064813
Split-gate memory having sector retirement with reduced current and method therefor Mar 8, 2016 Issued
Array ( [id] => 11087440 [patent_doc_number] => 20160284408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'MEMORY CELL AND CONTENT ADDRESSABLE MEMORY HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/063345 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3788 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15063345 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/063345
Content addressable memory and memory cell thereof Mar 6, 2016 Issued
Array ( [id] => 10992826 [patent_doc_number] => 20160189772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'SYSTEM AND A METHOD FOR DESIGNING A HYBRID MEMORY CELL WITH MEMRISTOR AND COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR' [patent_app_type] => utility [patent_app_number] => 15/062395 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/062395
System and a method for designing a hybrid memory cell with memristor and complementary metal-oxide semiconductor Mar 6, 2016 Issued
Array ( [id] => 11861714 [patent_doc_number] => 09741401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Reception circuit for reducing current and electronic apparatus including the same' [patent_app_type] => utility [patent_app_number] => 15/062961 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4075 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062961 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/062961
Reception circuit for reducing current and electronic apparatus including the same Mar 6, 2016 Issued
Array ( [id] => 11637654 [patent_doc_number] => 09659635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-23 [patent_title] => 'Memory array with bit-lines connected to different sub-arrays through jumper structures' [patent_app_type] => utility [patent_app_number] => 15/061573 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15061573 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/061573
Memory array with bit-lines connected to different sub-arrays through jumper structures Mar 3, 2016 Issued
Array ( [id] => 11391622 [patent_doc_number] => 09552870 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-24 [patent_title] => 'Memory includes transmitter for data synchronization transmission after a mode switch and method thereof' [patent_app_type] => utility [patent_app_number] => 15/059555 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15059555 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/059555
Memory includes transmitter for data synchronization transmission after a mode switch and method thereof Mar 2, 2016 Issued
Array ( [id] => 11063538 [patent_doc_number] => 20160260500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'MEMORY SELF-TESTING DEVICE AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/057203 [patent_app_country] => US [patent_app_date] => 2016-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15057203 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/057203
Self testing device for memory channels and memory control units and method thereof Feb 29, 2016 Issued
Array ( [id] => 11952795 [patent_doc_number] => 20170256946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'SYSTEM AND METHOD FOR CONTROLLING A MODULAR ENERGY MANAGEMENT SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/057151 [patent_app_country] => US [patent_app_date] => 2016-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15057151 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/057151
System and method for controlling a modular energy management system that controls an amount of power transferred from each of the energy modules to at least one load Feb 29, 2016 Issued
Array ( [id] => 11599510 [patent_doc_number] => 09646686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Reconfigurable circuit including row address replacement circuit for replacing defective address' [patent_app_type] => utility [patent_app_number] => 15/056083 [patent_app_country] => US [patent_app_date] => 2016-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15056083 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/056083
Reconfigurable circuit including row address replacement circuit for replacing defective address Feb 28, 2016 Issued
Array ( [id] => 11517265 [patent_doc_number] => 20170084339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'HIGH VOLTAGE SWITCH CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/054467 [patent_app_country] => US [patent_app_date] => 2016-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15054467 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/054467
High voltage switch circuit for switching high voltage without potential drop and semiconductor memory device including the same Feb 25, 2016 Issued
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