Search

Tuan V. Ho

Examiner (ID: 8114, Phone: (571)272-7365 , Office: P/2661 )

Most Active Art Unit
2661
Art Unit(s)
2613, 2615, 2602, 2712, 2612, 2606, 2661, 2622, 2604
Total Applications
2139
Issued Applications
1731
Pending Applications
101
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16347738 [patent_doc_number] => 20200312389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => TIMER FOR USE DUAL VOLTAGE SUPPLIES [patent_app_type] => utility [patent_app_number] => 16/370579 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370579 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370579
Timer for use dual voltage supplies Mar 28, 2019 Issued
Array ( [id] => 14905851 [patent_doc_number] => 20190296691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => LOWER POWER AUTO-ZEROING RECEIVER INCORPORATING CTLE, VGA, AND DFE [patent_app_type] => utility [patent_app_number] => 16/357609 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16357609 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/357609
Lower power auto-zeroing receiver incorporating CTLE, VGA, and DFE Mar 18, 2019 Issued
Array ( [id] => 14541747 [patent_doc_number] => 20190206495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/298591 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16298591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/298591
Memory device with a plurality of stacked memory core chips Mar 10, 2019 Issued
Array ( [id] => 16803113 [patent_doc_number] => 10998064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Resistive random access memory program and erase techniques and apparatus [patent_app_type] => utility [patent_app_number] => 16/291467 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291467 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291467
Resistive random access memory program and erase techniques and apparatus Mar 3, 2019 Issued
Array ( [id] => 16480523 [patent_doc_number] => 10855486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Dynamic control of smart home using wearable device [patent_app_type] => utility [patent_app_number] => 16/289051 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6275 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289051 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/289051
Dynamic control of smart home using wearable device Feb 27, 2019 Issued
Array ( [id] => 15461419 [patent_doc_number] => 20200043534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => HOLD TIME ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 16/287463 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/287463
Memory input hold time adjustment Feb 26, 2019 Issued
Array ( [id] => 15717133 [patent_doc_number] => 20200105334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/284971 [patent_app_country] => US [patent_app_date] => 2019-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16284971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/284971
Semiconductor devices for executing a column operation Feb 24, 2019 Issued
Array ( [id] => 16272033 [patent_doc_number] => 20200273521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SOURCE LINE CONFIGURATIONS FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/282749 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16282749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/282749
Source line management for memory cells with floating gates Feb 21, 2019 Issued
Array ( [id] => 15369201 [patent_doc_number] => 20200020365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/283655 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283655 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/283655
Memory device that performs a read operation and a test operation Feb 21, 2019 Issued
Array ( [id] => 16202035 [patent_doc_number] => 10727215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-28 [patent_title] => Three-dimensional memory device with logic signal routing through a memory die and methods of making the same [patent_app_type] => utility [patent_app_number] => 16/261869 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 42 [patent_no_of_words] => 19696 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261869 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/261869
Three-dimensional memory device with logic signal routing through a memory die and methods of making the same Jan 29, 2019 Issued
Array ( [id] => 16356246 [patent_doc_number] => 10796763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Method for programming a split-gate memory cell and corresponding memory device [patent_app_type] => utility [patent_app_number] => 16/256525 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4803 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256525 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/256525
Method for programming a split-gate memory cell and corresponding memory device Jan 23, 2019 Issued
Array ( [id] => 14572975 [patent_doc_number] => 20190214095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/242017 [patent_app_country] => US [patent_app_date] => 2019-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242017 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/242017
Power on fuse read operation in semiconductor storage device and operation method thereof Jan 7, 2019 Issued
Array ( [id] => 16094861 [patent_doc_number] => 20200201417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => MANAGEMENT OF POWER STATE TRANSITIONS OF A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 16/230299 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16230299 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/230299
Management of power state transitions of a memory sub-system Dec 20, 2018 Issued
Array ( [id] => 16308753 [patent_doc_number] => 10777563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Cell disturb prevention using a leaker device to reduce excess charge from an electronic device [patent_app_type] => utility [patent_app_number] => 16/228072 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228072 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228072
Cell disturb prevention using a leaker device to reduce excess charge from an electronic device Dec 19, 2018 Issued
Array ( [id] => 16739139 [patent_doc_number] => 10964807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => 3D semiconductor device with memory [patent_app_type] => utility [patent_app_number] => 16/226628 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 133 [patent_figures_cnt] => 149 [patent_no_of_words] => 25607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226628
3D semiconductor device with memory Dec 18, 2018 Issued
Array ( [id] => 14220653 [patent_doc_number] => 20190122711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/224305 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16224305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/224305
Three-dimensional semiconductor device with top dummy cells and bottom dummy cells and operating method thereof Dec 17, 2018 Issued
Array ( [id] => 14190767 [patent_doc_number] => 20190115089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => MEMORY DEVICE TO EXECUTE READ OPERATION USING READ TARGET VOLTAGE [patent_app_type] => utility [patent_app_number] => 16/210537 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16210537 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/210537
Memory device to execute read operation using read target voltage Dec 4, 2018 Issued
Array ( [id] => 16201724 [patent_doc_number] => 10726899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Semiconductor structures, memory cells and devices comprising ferroelectric materials, systems including same, and related methods [patent_app_type] => utility [patent_app_number] => 16/201478 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7317 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201478 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/201478
Semiconductor structures, memory cells and devices comprising ferroelectric materials, systems including same, and related methods Nov 26, 2018 Issued
Array ( [id] => 15369207 [patent_doc_number] => 20200020368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/200273 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200273 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/200273
Semiconductor device configured to generate a strobe signal having various patterns Nov 25, 2018 Issued
Array ( [id] => 16201748 [patent_doc_number] => 10726923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Bias scheme for dummy lines of data storage devices [patent_app_type] => utility [patent_app_number] => 16/198593 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 15511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16198593 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/198593
Bias scheme for dummy lines of data storage devices Nov 20, 2018 Issued
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