Search

Tuan V. Ho

Examiner (ID: 8114, Phone: (571)272-7365 , Office: P/2661 )

Most Active Art Unit
2661
Art Unit(s)
2613, 2615, 2602, 2712, 2612, 2606, 2661, 2622, 2604
Total Applications
2139
Issued Applications
1731
Pending Applications
101
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16047659 [patent_doc_number] => 10685708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Semiconductor device including volatile and non-volatile memory cells [patent_app_type] => utility [patent_app_number] => 16/059317 [patent_app_country] => US [patent_app_date] => 2018-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 8855 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16059317 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/059317
Semiconductor device including volatile and non-volatile memory cells Aug 8, 2018 Issued
Array ( [id] => 14542437 [patent_doc_number] => 20190206840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => MEMORY DEVICE INCLUDING HETEROGENEOUS VOLATILE MEMORY CHIPS AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/055199 [patent_app_country] => US [patent_app_date] => 2018-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16055199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/055199
Memory device including heterogeneous volatile memory chips and electronic device including the same Aug 5, 2018 Issued
Array ( [id] => 14675999 [patent_doc_number] => 20190237114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => MULTI-LEVEL SENSING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/044201 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16044201 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/044201
Multi-level sensing circuit configured to use a bit line charge Jul 23, 2018 Issued
Array ( [id] => 15286045 [patent_doc_number] => 10515691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Memory array with bit-lines connected to different sub-arrays through jumper structures [patent_app_type] => utility [patent_app_number] => 16/022831 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022831 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/022831
Memory array with bit-lines connected to different sub-arrays through jumper structures Jun 28, 2018 Issued
Array ( [id] => 15611061 [patent_doc_number] => 10586597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Programming of memory devices responsive to a stored representation of a programming voltage indicative of a programming efficiency [patent_app_type] => utility [patent_app_number] => 16/019631 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6821 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16019631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/019631
Programming of memory devices responsive to a stored representation of a programming voltage indicative of a programming efficiency Jun 26, 2018 Issued
Array ( [id] => 15759873 [patent_doc_number] => 10622063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Phase change memory device with reduced read disturb and method of making the same [patent_app_type] => utility [patent_app_number] => 16/019745 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 34 [patent_no_of_words] => 14482 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16019745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/019745
Phase change memory device with reduced read disturb and method of making the same Jun 26, 2018 Issued
Array ( [id] => 15856769 [patent_doc_number] => 10643677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Negative kick on bit line control transistors for faster bit line settling during sensing [patent_app_type] => utility [patent_app_number] => 16/018571 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 15213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16018571 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/018571
Negative kick on bit line control transistors for faster bit line settling during sensing Jun 25, 2018 Issued
Array ( [id] => 16322936 [patent_doc_number] => 10782899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Adaptive memory training for enhanced automotive boot [patent_app_type] => utility [patent_app_number] => 16/017758 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10613 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/017758
Adaptive memory training for enhanced automotive boot Jun 24, 2018 Issued
Array ( [id] => 14237549 [patent_doc_number] => 20190130947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => DATA STORAGE DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/014443 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16014443 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/014443
Data storage device and method of operating the same Jun 20, 2018 Issued
Array ( [id] => 15388395 [patent_doc_number] => 10535392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Integrated circuit memory device with write driver and method of operating same [patent_app_type] => utility [patent_app_number] => 16/014011 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7499 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16014011 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/014011
Integrated circuit memory device with write driver and method of operating same Jun 20, 2018 Issued
Array ( [id] => 13629297 [patent_doc_number] => 20180366201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/013349 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/013349
Semiconductor memory device capable of correctly reading data Jun 19, 2018 Issued
Array ( [id] => 14316429 [patent_doc_number] => 20190147918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/008877 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008877 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/008877
Memory device having selectable memory block pairs Jun 13, 2018 Issued
Array ( [id] => 15547165 [patent_doc_number] => 10573372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Sensing operations in memory by comparing inputs in a sense amplifier [patent_app_type] => utility [patent_app_number] => 15/994307 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5433 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/994307
Sensing operations in memory by comparing inputs in a sense amplifier May 30, 2018 Issued
Array ( [id] => 16218580 [patent_doc_number] => 10734403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Nonvolatile memory devices comprising a conductive line comprising portions having different profiles and methods of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/991309 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8880 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991309 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991309
Nonvolatile memory devices comprising a conductive line comprising portions having different profiles and methods of fabricating the same May 28, 2018 Issued
Array ( [id] => 14954817 [patent_doc_number] => 10438685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Memory device for preventing duplicate programming of fail address, and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/991733 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991733 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991733
Memory device for preventing duplicate programming of fail address, and operating method thereof May 28, 2018 Issued
Array ( [id] => 16218580 [patent_doc_number] => 10734403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Nonvolatile memory devices comprising a conductive line comprising portions having different profiles and methods of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/991309 [patent_app_country] => US [patent_app_date] => 2018-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8880 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991309 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/991309
Nonvolatile memory devices comprising a conductive line comprising portions having different profiles and methods of fabricating the same May 28, 2018 Issued
Array ( [id] => 15400729 [patent_doc_number] => 10541024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Memory system with signals on read lines not phase-aligned with Josephson transmission line (JTL) elements included in the write lines [patent_app_type] => utility [patent_app_number] => 15/990099 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6754 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15990099 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/990099
Memory system with signals on read lines not phase-aligned with Josephson transmission line (JTL) elements included in the write lines May 24, 2018 Issued
Array ( [id] => 14190693 [patent_doc_number] => 20190115052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => MEMORY CHIP, PACKAGE DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/984803 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15984803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/984803
Memory chip, package device having the memory chips, and operating method of package device May 20, 2018 Issued
Array ( [id] => 15108317 [patent_doc_number] => 10475488 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-12 [patent_title] => Memory device with an input signal management mechanism [patent_app_type] => utility [patent_app_number] => 15/975713 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6628 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975713 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/975713
Memory device with an input signal management mechanism May 8, 2018 Issued
Array ( [id] => 14366399 [patent_doc_number] => 10304511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-28 [patent_title] => Dual-edge trigger asynchronous clock generation and related methods [patent_app_type] => utility [patent_app_number] => 15/959669 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959669 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/959669
Dual-edge trigger asynchronous clock generation and related methods Apr 22, 2018 Issued
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