Tuan V. Ho

Array ( [id] => 14332607 [patent_doc_number] => 10297327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Sensing amplifier comprising fully depleted silicon-on-insulator transistors for reading a selected flash memory cell in an array of flash memory cells [patent_app_type] => utility [patent_app_number] => 15/952155 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 4797 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15952155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13363311 [patent_doc_number] => 20180233195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SEMICONDUCTOR DEVICES, CIRCUITS AND METHODS FOR READ AND/OR WRITE ASSIST OF AN SRAM CIRCUIT PORTION BASED ON VOLTAGE DETECTION AND/OR TEMPERATURE DETECTION CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/948928 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13071225 [patent_doc_number] => 10056398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-21 [patent_title] => Method of forming split-gate, twin-bit non-volatile memory cell [patent_app_type] => utility [patent_app_number] => 15/945659 [patent_app_country] => US [patent_app_date] => 2018-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 4225 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12895513 [patent_doc_number] => 20180190346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => METHOD AND APPARATUS FOR ENHANCING READ STABILITY OF A STATIC RANDOM ACCESS MEMORY CIRCUIT IN LOW VOLTAGE OPERATION [patent_app_type] => utility [patent_app_number] => 15/909261 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5985 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14079943 [patent_doc_number] => 20190088859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => MAGNETIC MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/905915 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15905915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14316493 [patent_doc_number] => 20190147950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => METHOD FOR PROGRAMMING RESISTIVE MEMORY CELL AND NONVOLATILE MEMORY DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 15/905699 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15905699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15856871 [patent_doc_number] => 10643730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => Adapting flash memory programming parameters for high endurance and steady performance [patent_app_type] => utility [patent_app_number] => 15/904893 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6785 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14190773 [patent_doc_number] => 20190115092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => NON-VOLATILE MEMORY DEVICE AND ERROR COMPENSATION METHOD FOR VERIFYING THE SAME [patent_app_type] => utility [patent_app_number] => 15/904447 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13819099 [patent_doc_number] => 10186323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Memory device to execute read operation using read target voltage [patent_app_type] => utility [patent_app_number] => 15/902399 [patent_app_country] => US [patent_app_date] => 2018-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 41 [patent_no_of_words] => 32671 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15902399 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14752575 [patent_doc_number] => 20190259461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => ERASING METHOD USED IN FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 15/902325 [patent_app_country] => US [patent_app_date] => 2018-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15902325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14827347 [patent_doc_number] => 10410684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Memory device with oxide semiconductor static random access memory and method for operating the same [patent_app_type] => utility [patent_app_number] => 15/900811 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15061003 [patent_doc_number] => 10460813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Nonvolatile memory devices providing reduced data line load [patent_app_type] => utility [patent_app_number] => 15/900023 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13282051 [patent_doc_number] => 10152613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Apparatus and method for physically unclonable function (PUF) for a memory array [patent_app_type] => utility [patent_app_number] => 15/898935 [patent_app_country] => US [patent_app_date] => 2018-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 20805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12849655 [patent_doc_number] => 20180175058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => METHOD OF CONTROLLING A SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/897811 [patent_app_country] => US [patent_app_date] => 2018-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15897811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13349145 [patent_doc_number] => 20180226112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => MRAM REFERENCE CELL WITH SHAPE ANISOTROPY TO ESTABLISH A WELL-DEFINED MAGNETIZATION ORIENTATION BETWEEN A REFERENCE LAYER AND A STORAGE LAYER [patent_app_type] => utility [patent_app_number] => 15/891233 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1902 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15891233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14676023 [patent_doc_number] => 20190237126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SEMICONDUCTOR DEVICE HAVING MODE REGISTER [patent_app_type] => utility [patent_app_number] => 15/882607 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12758833 [patent_doc_number] => 20180144779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => CONTROL LINES TO SENSING COMPONENTS [patent_app_type] => utility [patent_app_number] => 15/874117 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15138975 [patent_doc_number] => 10482969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Programming to a correctable amount of errors [patent_app_type] => utility [patent_app_number] => 15/874839 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 24517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13597785 [patent_doc_number] => 20180350441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/873081 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12758908 [patent_doc_number] => 20180144804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => Sensing Amplifier Comprising Voltage Offset Circuitry For Use In Flash Memory Devices [patent_app_type] => utility [patent_app_number] => 15/873872 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873872 [rel_patent_id] =>[rel_patent_doc_number] =>)