Search

Tuan V. Thai

Examiner (ID: 19385, Phone: (571)272-4187 , Office: P/2135 )

Most Active Art Unit
2135
Art Unit(s)
2185, 2186, 2135, 2752, 2318
Total Applications
1739
Issued Applications
1522
Pending Applications
71
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9980392 [patent_doc_number] => 09026721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Managing defective areas of memory' [patent_app_type] => utility [patent_app_number] => 13/793036 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 13166 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793036 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/793036
Managing defective areas of memory Mar 10, 2013 Issued
Array ( [id] => 9257718 [patent_doc_number] => 08621158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Information processor system' [patent_app_type] => utility [patent_app_number] => 13/782158 [patent_app_country] => US [patent_app_date] => 2013-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 17257 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13782158 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/782158
Information processor system Feb 28, 2013 Issued
Array ( [id] => 8893645 [patent_doc_number] => 20130166829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'Fast Block Device and Methodology' [patent_app_type] => utility [patent_app_number] => 13/769455 [patent_app_country] => US [patent_app_date] => 2013-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8855 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13769455 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/769455
Fast block device and methodology Feb 17, 2013 Issued
Array ( [id] => 9200262 [patent_doc_number] => 20130339577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'METHOD FOR READING A MULTILEVEL CELL IN A NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/762874 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762874
Method for reading a multilevel cell in a non-volatile memory device Feb 7, 2013 Issued
Array ( [id] => 8929723 [patent_doc_number] => 20130185483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'DATA STORAGE SYSTEM, MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/739417 [patent_app_country] => US [patent_app_date] => 2013-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739417 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/739417
DATA STORAGE SYSTEM, MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND METHOD OF OPERATING THE SAME Jan 10, 2013 Abandoned
Array ( [id] => 9604791 [patent_doc_number] => 20140201473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'HOST CONTROLLED ENABLEMENT OF AUTOMATIC BACKGROUND OPERATIONS IN A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/739453 [patent_app_country] => US [patent_app_date] => 2013-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3736 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739453 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/739453
Host controlled enablement of automatic background operations in a memory device Jan 10, 2013 Issued
Array ( [id] => 9599084 [patent_doc_number] => 20140195765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'IMPLEMENTING USER MODE FOREIGN DEVICE ATTACHMENT TO MEMORY CHANNEL' [patent_app_type] => utility [patent_app_number] => 13/738035 [patent_app_country] => US [patent_app_date] => 2013-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5677 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13738035 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/738035
Implementing user mode foreign device attachment to memory channel Jan 9, 2013 Issued
Array ( [id] => 10575954 [patent_doc_number] => 09298600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Method and apparatus for dynamically allocating memory address space between physical memories' [patent_app_type] => utility [patent_app_number] => 13/738709 [patent_app_country] => US [patent_app_date] => 2013-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13738709 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/738709
Method and apparatus for dynamically allocating memory address space between physical memories Jan 9, 2013 Issued
Array ( [id] => 10596012 [patent_doc_number] => 09317100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Accelerated cache rinse when preparing a power state transition' [patent_app_type] => utility [patent_app_number] => 13/738378 [patent_app_country] => US [patent_app_date] => 2013-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3300 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13738378 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/738378
Accelerated cache rinse when preparing a power state transition Jan 9, 2013 Issued
Array ( [id] => 10976931 [patent_doc_number] => 20140379967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'CLOCK SIGNAL GENERATOR FOR A DIGITAL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/370915 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2879 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14370915 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/370915
CLOCK SIGNAL GENERATOR FOR A DIGITAL CIRCUIT Jan 8, 2013 Abandoned
Array ( [id] => 10046506 [patent_doc_number] => 09086903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Managing virtual hard disk snapshots' [patent_app_type] => utility [patent_app_number] => 13/737460 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6525 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737460 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/737460
Managing virtual hard disk snapshots Jan 8, 2013 Issued
Array ( [id] => 10098596 [patent_doc_number] => 09134908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Logical volume space sharing' [patent_app_type] => utility [patent_app_number] => 13/737929 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4786 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737929 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/737929
Logical volume space sharing Jan 8, 2013 Issued
Array ( [id] => 10530418 [patent_doc_number] => 09256554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Progress recording method and recovering method for encoding operation on storage device' [patent_app_type] => utility [patent_app_number] => 13/736092 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5315 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13736092 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/736092
Progress recording method and recovering method for encoding operation on storage device Jan 7, 2013 Issued
Array ( [id] => 9599083 [patent_doc_number] => 20140195764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'MEMORY DEVICE HAVING AN ADAPTABLE NUMBER OF OPEN ROWS' [patent_app_type] => utility [patent_app_number] => 13/736662 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13736662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/736662
Memory device having an adaptable number of open rows Jan 7, 2013 Issued
Array ( [id] => 10034443 [patent_doc_number] => 09075762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Setting copy permissions for target data in a copy relationship' [patent_app_type] => utility [patent_app_number] => 13/734755 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6073 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13734755 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/734755
Setting copy permissions for target data in a copy relationship Jan 3, 2013 Issued
Array ( [id] => 8868103 [patent_doc_number] => 20130151806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'TIERED STORAGE POOL MANAGEMENT AND CONTROL FOR LOOSELY COUPLED MULTIPLE STORAGE ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/733610 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 16540 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733610 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733610
Tiered storage pool management and control for loosely coupled multiple storage environment Jan 2, 2013 Issued
Array ( [id] => 10544279 [patent_doc_number] => 09269411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Organizing data in a hybrid memory for search operations' [patent_app_type] => utility [patent_app_number] => 13/730034 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730034 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730034
Organizing data in a hybrid memory for search operations Dec 27, 2012 Issued
Array ( [id] => 9571478 [patent_doc_number] => 20140189191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'APPARATUS AND METHOD FOR MEMORY-MAPPED REGISTER CACHING' [patent_app_type] => utility [patent_app_number] => 13/730030 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15604 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730030 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730030
Apparatus and method for memory-mapped register caching Dec 27, 2012 Issued
Array ( [id] => 9257712 [patent_doc_number] => 08621152 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-31 [patent_title] => 'Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access' [patent_app_type] => utility [patent_app_number] => 13/724864 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7266 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724864 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/724864
Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access Dec 20, 2012 Issued
Array ( [id] => 9781259 [patent_doc_number] => 08856480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Mechanism for enabling full data bus utilization without increasing data granularity' [patent_app_type] => utility [patent_app_number] => 13/720585 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11723 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13720585 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/720585
Mechanism for enabling full data bus utilization without increasing data granularity Dec 18, 2012 Issued
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