Search

Tucker J. Wright

Examiner (ID: 5553, Phone: (571)270-3234 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2891, 2896
Total Applications
1135
Issued Applications
862
Pending Applications
100
Abandoned Applications
202

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14110633 [patent_doc_number] => 20190096992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/203669 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203669
High voltage metal oxide semiconductor device and manufacturing method thereof Nov 28, 2018 Issued
Array ( [id] => 14024647 [patent_doc_number] => 20190074317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => IMAGE SENSORS WITH VERTICALLY STACKED PHOTODIODES AND VERTICAL TRANSFER GATES [patent_app_type] => utility [patent_app_number] => 16/182766 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16182766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/182766
Image sensors with vertically stacked photodiodes and vertical transfer gates Nov 6, 2018 Issued
Array ( [id] => 16609469 [patent_doc_number] => 10910485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Semiconductor device having semiconductor regions with an impurity concentration distribution which decreases from a respective peak toward different semiconductor layers [patent_app_type] => utility [patent_app_number] => 16/171644 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 18963 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171644
Semiconductor device having semiconductor regions with an impurity concentration distribution which decreases from a respective peak toward different semiconductor layers Oct 25, 2018 Issued
Array ( [id] => 13996611 [patent_doc_number] => 20190067463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/171680 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171680 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171680
Semiconductor device having semiconductor regions of different conductivity types provided at a predetermined interval along a first direction Oct 25, 2018 Issued
Array ( [id] => 16609469 [patent_doc_number] => 10910485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Semiconductor device having semiconductor regions with an impurity concentration distribution which decreases from a respective peak toward different semiconductor layers [patent_app_type] => utility [patent_app_number] => 16/171644 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 18963 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171644
Semiconductor device having semiconductor regions with an impurity concentration distribution which decreases from a respective peak toward different semiconductor layers Oct 25, 2018 Issued
Array ( [id] => 16609469 [patent_doc_number] => 10910485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Semiconductor device having semiconductor regions with an impurity concentration distribution which decreases from a respective peak toward different semiconductor layers [patent_app_type] => utility [patent_app_number] => 16/171644 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 18963 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171644
Semiconductor device having semiconductor regions with an impurity concentration distribution which decreases from a respective peak toward different semiconductor layers Oct 25, 2018 Issued
Array ( [id] => 16609469 [patent_doc_number] => 10910485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Semiconductor device having semiconductor regions with an impurity concentration distribution which decreases from a respective peak toward different semiconductor layers [patent_app_type] => utility [patent_app_number] => 16/171644 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 18963 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171644
Semiconductor device having semiconductor regions with an impurity concentration distribution which decreases from a respective peak toward different semiconductor layers Oct 25, 2018 Issued
Array ( [id] => 14232615 [patent_doc_number] => 20190128480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => LED LIGHT SOURCE MODULE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/145904 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145904 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145904
LED light source module and method for manufacturing the same Sep 27, 2018 Issued
Array ( [id] => 13879301 [patent_doc_number] => 20190035991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => LED PACKAGE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/145222 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145222 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145222
LED package and method for manufacturing the same Sep 27, 2018 Issued
Array ( [id] => 15717751 [patent_doc_number] => 20200105643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => INTEGRATED HEAT SPREADER WITH MULTIPLE CHANNELS FOR MULTICHIP PACKAGES [patent_app_type] => utility [patent_app_number] => 16/144584 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16144584 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/144584
Integrated heat spreader with multiple channels for multichip packages Sep 26, 2018 Issued
Array ( [id] => 15688011 [patent_doc_number] => 20200098669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => THERMAL MANAGEMENT SOLUTIONS FOR SUBSTRATES IN INTEGRATED CIRCUIT PACKAGES [patent_app_type] => utility [patent_app_number] => 16/141746 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141746 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/141746
Thermal management solutions for substrates in integrated circuit packages Sep 24, 2018 Issued
Array ( [id] => 17978645 [patent_doc_number] => 11495517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Packaging method and joint technology for an electronic device [patent_app_type] => utility [patent_app_number] => 16/647214 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 43 [patent_no_of_words] => 20258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16647214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/647214
Packaging method and joint technology for an electronic device Sep 16, 2018 Issued
Array ( [id] => 13848045 [patent_doc_number] => 20190027507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => DISPLAY DEVICE, DISPLAY MODULE, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/126360 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126360 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/126360
Display device, display module, and electronic device Sep 9, 2018 Issued
Array ( [id] => 13785617 [patent_doc_number] => 20190006347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/123349 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16123349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/123349
Method of manufacturing a semiconductor device Sep 5, 2018 Issued
Array ( [id] => 17683401 [patent_doc_number] => 11367666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Clip, lead frame, and substrate used in semiconductor package having engraved pattern formed thereon and the semiconductor package comprising the same [patent_app_type] => utility [patent_app_number] => 16/638135 [patent_app_country] => US [patent_app_date] => 2018-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5245 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16638135 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/638135
Clip, lead frame, and substrate used in semiconductor package having engraved pattern formed thereon and the semiconductor package comprising the same Aug 22, 2018 Issued
Array ( [id] => 16042693 [patent_doc_number] => 10683205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Release chemical protection for integrated complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) devices [patent_app_type] => utility [patent_app_number] => 16/101353 [patent_app_country] => US [patent_app_date] => 2018-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5423 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16101353 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/101353
Release chemical protection for integrated complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) devices Aug 9, 2018 Issued
Array ( [id] => 15503411 [patent_doc_number] => 20200051894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => THERMAL ASSEMBLIES FOR MULTI-CHIP PACKAGES [patent_app_type] => utility [patent_app_number] => 16/100406 [patent_app_country] => US [patent_app_date] => 2018-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16100406 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/100406
Thermal assemblies for multi-chip packages Aug 9, 2018 Issued
Array ( [id] => 16249521 [patent_doc_number] => 10748896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Method for fabricating semiconductor device including contact bars having narrower portions [patent_app_type] => utility [patent_app_number] => 16/049084 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16049084 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/049084
Method for fabricating semiconductor device including contact bars having narrower portions Jul 29, 2018 Issued
Array ( [id] => 13740953 [patent_doc_number] => 20180374946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => METHODS OF FORMING A BULK FIELD EFFECT TRANSISTOR (FET) WITH SUB-SOURCE/DRAIN ISOLATION LAYERS AND THE RESULTING STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/046368 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046368 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046368
Methods of forming a bulk field effect transistor (FET) with sub-source/drain isolation layers and the resulting structures Jul 25, 2018 Issued
Array ( [id] => 15547965 [patent_doc_number] => 10573775 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-25 [patent_title] => Bi CMOS pixel [patent_app_type] => utility [patent_app_number] => 16/044882 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 3954 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16044882 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/044882
Bi CMOS pixel Jul 24, 2018 Issued
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