Tucker J. Wright

Array ( [id] => 4876617 [patent_doc_number] => 20080150000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'MEMORY SYSTEM WITH SELECT GATE ERASE' [patent_app_type] => utility [patent_app_number] => 11/614839 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150000.pdf [firstpage_image] =>[orig_patent_app_number] => 11614839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5016296 [patent_doc_number] => 20070259505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'NON-VOLATILE MEMORY DEVICES AND METHODS FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/613329 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3307 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20070259505.pdf [firstpage_image] =>[orig_patent_app_number] => 11613329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5019517 [patent_doc_number] => 20070145483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/640929 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145483.pdf [firstpage_image] =>[orig_patent_app_number] => 11640929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4783915 [patent_doc_number] => 20080137244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Electrostatic discharge protection circuit' [patent_app_type] => utility [patent_app_number] => 11/637108 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2121 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20080137244.pdf [firstpage_image] =>[orig_patent_app_number] => 11637108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5250563 [patent_doc_number] => 20070132019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'DMOS transistor with optimized periphery structure' [patent_app_type] => utility [patent_app_number] => 11/636668 [patent_app_country] => US [patent_app_date] => 2006-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1821 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20070132019.pdf [firstpage_image] =>[orig_patent_app_number] => 11636668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5066657 [patent_doc_number] => 20070187758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'SB-MOSFET (Schottky barrier metal-oxide-semiconductor field effect transistor) with low barrier height and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 11/635179 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2704 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20070187758.pdf [firstpage_image] =>[orig_patent_app_number] => 11635179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4782624 [patent_doc_number] => 20080135953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Noise reduction in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/635709 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7203 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20080135953.pdf [firstpage_image] =>[orig_patent_app_number] => 11635709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4829260 [patent_doc_number] => 20080128791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Memory cells with improved program/erase windows' [patent_app_type] => utility [patent_app_number] => 11/633719 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3391 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20080128791.pdf [firstpage_image] =>[orig_patent_app_number] => 11633719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4820686 [patent_doc_number] => 20080121983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Gate and method of forming the same, and memory device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/606899 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20080121983.pdf [firstpage_image] =>[orig_patent_app_number] => 11606899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7811666 [patent_doc_number] => 08134198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/563069 [patent_app_country] => US [patent_app_date] => 2006-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12940 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/134/08134198.pdf [firstpage_image] =>[orig_patent_app_number] => 11563069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 239963 [patent_doc_number] => 07592682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Optical waveguide and photoreceptor' [patent_app_type] => utility [patent_app_number] => 11/562519 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 60 [patent_no_of_words] => 9489 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/592/07592682.pdf [firstpage_image] =>[orig_patent_app_number] => 11562519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5092993 [patent_doc_number] => 20070114602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/562708 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20070114602.pdf [firstpage_image] =>[orig_patent_app_number] => 11562708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4896834 [patent_doc_number] => 20080116447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'NON-VOLATILE MEMORY TRANSISTOR WITH QUANTUM WELL CHARGE TRAP' [patent_app_type] => utility [patent_app_number] => 11/561808 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2357 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20080116447.pdf [firstpage_image] =>[orig_patent_app_number] => 11561808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5116796 [patent_doc_number] => 20070138510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Gate array' [patent_app_type] => utility [patent_app_number] => 11/600829 [patent_app_country] => US [patent_app_date] => 2006-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3376 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138510.pdf [firstpage_image] =>[orig_patent_app_number] => 11600829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 174231 [patent_doc_number] => 07659611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Vertical power semiconductor component, semiconductor device and methods for the production thereof' [patent_app_type] => utility [patent_app_number] => 11/560158 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 6738 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/659/07659611.pdf [firstpage_image] =>[orig_patent_app_number] => 11560158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 124127 [patent_doc_number] => 07705427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Integrated circuit comprising a gradually doped bipolar transistor' [patent_app_type] => utility [patent_app_number] => 11/560228 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/705/07705427.pdf [firstpage_image] =>[orig_patent_app_number] => 11560228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 311371 [patent_doc_number] => 07528402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Electrically rewritable non-volatile memory element' [patent_app_type] => utility [patent_app_number] => 11/594879 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6588 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/528/07528402.pdf [firstpage_image] =>[orig_patent_app_number] => 11594879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4673398 [patent_doc_number] => 20080211026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Coupling well structure for improving HVMOS performance' [patent_app_type] => utility [patent_app_number] => 11/594508 [patent_app_country] => US [patent_app_date] => 2006-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3269 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20080211026.pdf [firstpage_image] =>[orig_patent_app_number] => 11594508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5444254 [patent_doc_number] => 20090045480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/094499 [patent_app_country] => US [patent_app_date] => 2006-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12404 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20090045480.pdf [firstpage_image] =>[orig_patent_app_number] => 12094499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4576681 [patent_doc_number] => 07829955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/554659 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 55 [patent_no_of_words] => 9398 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/829/07829955.pdf [firstpage_image] =>[orig_patent_app_number] => 11554659 [rel_patent_id] =>[rel_patent_doc_number] =>)