Search

Ubachukwu A. Odunukwe

Examiner (ID: 15798, Phone: (571)272-8927 , Office: P/2654 )

Most Active Art Unit
2654
Art Unit(s)
2654
Total Applications
314
Issued Applications
254
Pending Applications
0
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19654477 [patent_doc_number] => 12176277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Package substrate and package structure [patent_app_type] => utility [patent_app_number] => 17/676862 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6666 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676862 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/676862
Package substrate and package structure Feb 21, 2022 Issued
Array ( [id] => 19376705 [patent_doc_number] => 12068285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Stacked die structure and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/676233 [patent_app_country] => US [patent_app_date] => 2022-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 7842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/676233
Stacked die structure and method of fabricating the same Feb 20, 2022 Issued
Array ( [id] => 17630651 [patent_doc_number] => 20220165666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => LASER-FORMED INTERCONNECTS FOR REDUNDANT DEVICES [patent_app_type] => utility [patent_app_number] => 17/670810 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670810
Laser-formed interconnects for redundant devices Feb 13, 2022 Issued
Array ( [id] => 18570539 [patent_doc_number] => 20230260876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => MONOLITHIC CONDUCTIVE COLUMN IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS [patent_app_type] => utility [patent_app_number] => 17/670391 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670391 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670391
Monolithic conductive column in a semiconductor device and associated methods Feb 10, 2022 Issued
Array ( [id] => 18570540 [patent_doc_number] => 20230260877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => MONOLITHIC CONDUCTIVE CYLINDER IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS [patent_app_type] => utility [patent_app_number] => 17/670393 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670393
Monolithic conductive cylinder in a semiconductor device and associated methods Feb 10, 2022 Issued
Array ( [id] => 17949411 [patent_doc_number] => 20220336430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => INTEGRATED CIRCUIT PACKAGE WITH DECOUPLING CAPACITORS [patent_app_type] => utility [patent_app_number] => 17/591084 [patent_app_country] => US [patent_app_date] => 2022-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/591084
Integrated circuit package with decoupling capacitors Feb 1, 2022 Issued
Array ( [id] => 18481208 [patent_doc_number] => 11694963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Semiconductor device and semiconductor package including the same [patent_app_type] => utility [patent_app_number] => 17/589301 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 8795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589301 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589301
Semiconductor device and semiconductor package including the same Jan 30, 2022 Issued
Array ( [id] => 18008635 [patent_doc_number] => 20220367402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/648425 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648425 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648425
Semiconductor package Jan 19, 2022 Issued
Array ( [id] => 18229848 [patent_doc_number] => 20230068842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS [patent_app_type] => utility [patent_app_number] => 17/580368 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580368 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580368
Semiconductor package including stacked semiconductor chips Jan 19, 2022 Issued
Array ( [id] => 17583101 [patent_doc_number] => 20220139956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/578965 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578965
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Jan 18, 2022 Abandoned
Array ( [id] => 18447152 [patent_doc_number] => 11682729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Methods of forming air spacers in semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/576725 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/576725
Methods of forming air spacers in semiconductor devices Jan 13, 2022 Issued
Array ( [id] => 18874887 [patent_doc_number] => 11862710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Vertical transistor including symmetrical source/drain extension junctions [patent_app_type] => utility [patent_app_number] => 17/569669 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7711 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569669 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569669
Vertical transistor including symmetrical source/drain extension junctions Jan 5, 2022 Issued
Array ( [id] => 18416054 [patent_doc_number] => 11670602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Secure integrated-circuit systems [patent_app_type] => utility [patent_app_number] => 17/569085 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 8051 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569085
Secure integrated-circuit systems Jan 4, 2022 Issued
Array ( [id] => 17551555 [patent_doc_number] => 20220122897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => Integrated Circuit Package and Method [patent_app_type] => utility [patent_app_number] => 17/567519 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567519 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567519
Integrated circuit package and method Jan 2, 2022 Issued
Array ( [id] => 19063145 [patent_doc_number] => 11942396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Heterogeneous integration semiconductor package structure [patent_app_type] => utility [patent_app_number] => 17/564219 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 5471 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564219
Heterogeneous integration semiconductor package structure Dec 28, 2021 Issued
Array ( [id] => 18040134 [patent_doc_number] => 20220384351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/562477 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562477 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562477
Semiconductor device and semiconductor package including the same Dec 26, 2021 Issued
Array ( [id] => 18473117 [patent_doc_number] => 20230207405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => ULTRA LOW LOSS ROUTING BETWEEN GLASS CORES [patent_app_type] => utility [patent_app_number] => 17/561722 [patent_app_country] => US [patent_app_date] => 2021-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561722
ULTRA LOW LOSS ROUTING BETWEEN GLASS CORES Dec 23, 2021 Pending
Array ( [id] => 18473119 [patent_doc_number] => 20230207407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => PLATE-UP HYBRID STRUCTURES USING MODIFIED GLASS PATTERNING PROCESSES [patent_app_type] => utility [patent_app_number] => 17/561734 [patent_app_country] => US [patent_app_date] => 2021-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561734 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561734
PLATE-UP HYBRID STRUCTURES USING MODIFIED GLASS PATTERNING PROCESSES Dec 23, 2021 Pending
Array ( [id] => 18473124 [patent_doc_number] => 20230207412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => TECHNIQUES TO ENABLE A FLIP CHIP UNDERFILL EXCLUSION ZONE [patent_app_type] => utility [patent_app_number] => 17/561432 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561432 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561432
TECHNIQUES TO ENABLE A FLIP CHIP UNDERFILL EXCLUSION ZONE Dec 22, 2021 Pending
Array ( [id] => 18473151 [patent_doc_number] => 20230207439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => PACKAGE ARCHITECTURE WITH IN-GLASS BLIND AND THROUGH CAVITIES TO ACCOMMODATE DIES [patent_app_type] => utility [patent_app_number] => 17/561533 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561533
PACKAGE ARCHITECTURE WITH IN-GLASS BLIND AND THROUGH CAVITIES TO ACCOMMODATE DIES Dec 22, 2021 Abandoned
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