Upendra Roy

Array ( [id] => 2443744 [patent_doc_number] => 04745079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-17 [patent_title] => 'Method for fabricating MOS transistors having gates with different work functions' [patent_app_type] => 1 [patent_app_number] => 7/031299 [patent_app_country] => US [patent_app_date] => 1987-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3133 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/745/04745079.pdf [firstpage_image] =>[orig_patent_app_number] => 031299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2478465 [patent_doc_number] => 04820359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-11 [patent_title] => 'Process for thermally stress-relieving a tube' [patent_app_type] => 1 [patent_app_number] => 7/024941 [patent_app_country] => US [patent_app_date] => 1987-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6120 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/820/04820359.pdf [firstpage_image] =>[orig_patent_app_number] => 024941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2392120 [patent_doc_number] => 04782031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-01 [patent_title] => 'Method of making GaAs MOSFET with low source resistance yet having satisfactory leakage current by ion-implantation' [patent_app_type] => 1 [patent_app_number] => 7/022597 [patent_app_country] => US [patent_app_date] => 1987-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3086 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/782/04782031.pdf [firstpage_image] =>[orig_patent_app_number] => 022597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2422867 [patent_doc_number] => 04762802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-09 [patent_title] => 'Method for preventing latchup in CMOS devices' [patent_app_type] => 1 [patent_app_number] => 7/020268 [patent_app_country] => US [patent_app_date] => 1987-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2749 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/762/04762802.pdf [firstpage_image] =>[orig_patent_app_number] => 020268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2452553 [patent_doc_number] => 04766086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-23 [patent_title] => 'Method of gettering a semiconductor device and forming an isolation region therein' [patent_app_type] => 1 [patent_app_number] => 7/020758 [patent_app_country] => US [patent_app_date] => 1987-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3012 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/766/04766086.pdf [firstpage_image] =>[orig_patent_app_number] => 020758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2387919 [patent_doc_number] => 04753895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-06-28 [patent_title] => 'Method of forming low leakage CMOS device on insulating substrate' [patent_app_type] => 1 [patent_app_number] => 7/017498 [patent_app_country] => US [patent_app_date] => 1987-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4906 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/753/04753895.pdf [firstpage_image] =>[orig_patent_app_number] => 017498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2387730 [patent_doc_number] => 04777146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-11 [patent_title] => 'Fabrication process involving semi-insulating material' [patent_app_type] => 1 [patent_app_number] => 7/042397 [patent_app_country] => US [patent_app_date] => 1987-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3190 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/777/04777146.pdf [firstpage_image] =>[orig_patent_app_number] => 042397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2444517 [patent_doc_number] => 04740478 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-04-26 [patent_title] => 'Integrated circuit method using double implant doping' [patent_app_type] => 1 [patent_app_number] => 7/008991 [patent_app_country] => US [patent_app_date] => 1987-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 9301 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/740/04740478.pdf [firstpage_image] =>[orig_patent_app_number] => 008991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2413367 [patent_doc_number] => 04786608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-22 [patent_title] => 'Technique for forming electric field shielding layer in oxygen-implanted silicon substrate' [patent_app_type] => 1 [patent_app_number] => 6/947749 [patent_app_country] => US [patent_app_date] => 1986-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3088 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/786/04786608.pdf [firstpage_image] =>[orig_patent_app_number] => 947749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2382626 [patent_doc_number] => 04752592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-06-21 [patent_title] => 'Annealing method for compound semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 6/935827 [patent_app_country] => US [patent_app_date] => 1986-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 2824 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/752/04752592.pdf [firstpage_image] =>[orig_patent_app_number] => 935827 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2443853 [patent_doc_number] => 04749660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-06-07 [patent_title] => 'Method of making an article comprising a buried SiO.sub.2 layer' [patent_app_type] => 1 [patent_app_number] => 6/935273 [patent_app_country] => US [patent_app_date] => 1986-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3161 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/749/04749660.pdf [firstpage_image] =>[orig_patent_app_number] => 935273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2555626 [patent_doc_number] => 04816421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-28 [patent_title] => 'Method of making a heteroepitaxial structure by mesotaxy induced by buried implantation' [patent_app_type] => 1 [patent_app_number] => 6/934160 [patent_app_country] => US [patent_app_date] => 1986-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5026 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/816/04816421.pdf [firstpage_image] =>[orig_patent_app_number] => 934160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2387940 [patent_doc_number] => 04753896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-06-28 [patent_title] => 'Sidewall channel stop process' [patent_app_type] => 1 [patent_app_number] => 6/933500 [patent_app_country] => US [patent_app_date] => 1986-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 4400 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/753/04753896.pdf [firstpage_image] =>[orig_patent_app_number] => 933500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2417513 [patent_doc_number] => 04771010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-09-13 [patent_title] => 'Energy beam induced layer disordering (EBILD)' [patent_app_type] => 1 [patent_app_number] => 6/933666 [patent_app_country] => US [patent_app_date] => 1986-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 10516 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/771/04771010.pdf [firstpage_image] =>[orig_patent_app_number] => 933666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2388462 [patent_doc_number] => 04764478 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-16 [patent_title] => 'Method of manufacturing MOS transistor by dual species implantation and rapid annealing' [patent_app_type] => 1 [patent_app_number] => 6/932523 [patent_app_country] => US [patent_app_date] => 1986-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2578 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/764/04764478.pdf [firstpage_image] =>[orig_patent_app_number] => 932523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2552325 [patent_doc_number] => 04836788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-06 [patent_title] => 'Production of solid-state image pick-up device with uniform distribution of dopants' [patent_app_type] => 1 [patent_app_number] => 6/927161 [patent_app_country] => US [patent_app_date] => 1986-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4803 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/836/04836788.pdf [firstpage_image] =>[orig_patent_app_number] => 927161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2450441 [patent_doc_number] => 04732867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-03-22 [patent_title] => 'Method of forming alignment marks in sapphire' [patent_app_type] => 1 [patent_app_number] => 6/925983 [patent_app_country] => US [patent_app_date] => 1986-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1090 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/732/04732867.pdf [firstpage_image] =>[orig_patent_app_number] => 925983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2415588 [patent_doc_number] => 04746627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-24 [patent_title] => 'Method of making complementary GaAs heterojunction transistors' [patent_app_type] => 1 [patent_app_number] => 6/924883 [patent_app_country] => US [patent_app_date] => 1986-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3637 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/746/04746627.pdf [firstpage_image] =>[orig_patent_app_number] => 924883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2526139 [patent_doc_number] => 04797372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-10 [patent_title] => 'Method of making a merge bipolar and complementary metal oxide semiconductor transistor device' [patent_app_type] => 1 [patent_app_number] => 6/922961 [patent_app_country] => US [patent_app_date] => 1986-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 2984 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/797/04797372.pdf [firstpage_image] =>[orig_patent_app_number] => 922961 [rel_patent_id] =>[rel_patent_doc_number] =>)