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Uyen Tran Smet

Examiner (ID: 12313, Phone: (571)272-2267 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
768
Issued Applications
665
Pending Applications
72
Abandoned Applications
42

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20017871 [patent_doc_number] => 20250156093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => FLASH MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 19/023324 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19023324 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/023324
FLASH MEMORY CONTROLLER Jan 15, 2025 Pending
Array ( [id] => 20010850 [patent_doc_number] => 20250149072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => Assemblies Comprising Memory Cells and Select Gates; and Methods of Forming Assemblies [patent_app_type] => utility [patent_app_number] => 19/013290 [patent_app_country] => US [patent_app_date] => 2025-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19013290 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/013290
Assemblies Comprising Memory Cells and Select Gates; and Methods of Forming Assemblies Jan 7, 2025 Pending
Array ( [id] => 20324357 [patent_doc_number] => 20250336445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => MEMORIES, OPERATION METHODS THEREOF, AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 19/010908 [patent_app_country] => US [patent_app_date] => 2025-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19010908 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/010908
MEMORIES, OPERATION METHODS THEREOF, AND MEMORY SYSTEMS Jan 5, 2025 Pending
Array ( [id] => 20696683 [patent_doc_number] => 20260128096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-07 [patent_title] => BIAS CIRCUIT FOR NON-VOLATILE MEMORY ARRAY IN A NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/991295 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18991295 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/991295
BIAS CIRCUIT FOR NON-VOLATILE MEMORY ARRAY IN A NEURAL NETWORK Dec 19, 2024 Pending
Array ( [id] => 20291071 [patent_doc_number] => 20250316314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => MEMORY DEVICE PERFORMING IN-MEMORY COMPUTING [patent_app_type] => utility [patent_app_number] => 18/985791 [patent_app_country] => US [patent_app_date] => 2024-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18985791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/985791
MEMORY DEVICE PERFORMING IN-MEMORY COMPUTING Dec 17, 2024 Pending
Array ( [id] => 20411318 [patent_doc_number] => 20250380428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => SELF-SELECTING MEMORY MATERIAL, DEVICE, AND ELECTRONIC DEVICE INCLUDING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/980651 [patent_app_country] => US [patent_app_date] => 2024-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18980651 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/980651
SELF-SELECTING MEMORY MATERIAL, DEVICE, AND ELECTRONIC DEVICE INCLUDING THE MEMORY DEVICE Dec 12, 2024 Pending
Array ( [id] => 19865962 [patent_doc_number] => 20250104748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY DEVICE, OPERATION METHOD OF MEMORY DEVICE, AND PAGE BUFFER INCLUDED IN MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/971939 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/971939
MEMORY DEVICE, OPERATION METHOD OF MEMORY DEVICE, AND PAGE BUFFER INCLUDED IN MEMORY DEVICE Dec 5, 2024 Pending
Array ( [id] => 20739480 [patent_doc_number] => 20260148787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-28 [patent_title] => OUTER PRODUCT ENGINE WITH CAPACITIVE DEVICE ARRAY [patent_app_type] => utility [patent_app_number] => 18/960756 [patent_app_country] => US [patent_app_date] => 2024-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18960756 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/960756
OUTER PRODUCT ENGINE WITH CAPACITIVE DEVICE ARRAY Nov 25, 2024 Pending
Array ( [id] => 19834272 [patent_doc_number] => 20250086058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => READ CALIBRATION BY SECTOR OF MEMORY [patent_app_type] => utility [patent_app_number] => 18/954008 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/954008
READ CALIBRATION BY SECTOR OF MEMORY Nov 19, 2024 Pending
Array ( [id] => 19757795 [patent_doc_number] => 20250046360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => CLOCK SIGNAL GENERATION CIRCUIT AND METHOD, AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/923615 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923615 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/923615
CLOCK SIGNAL GENERATION CIRCUIT AND METHOD, AND MEMORY Oct 21, 2024 Pending
Array ( [id] => 20019311 [patent_doc_number] => 20250157533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => VERTICALLY INTEGRATED NEURAL NETWORK COMPUTING SYSTEM AND ASSOCIATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/908821 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18908821 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/908821
VERTICALLY INTEGRATED NEURAL NETWORK COMPUTING SYSTEM AND ASSOCIATED SYSTEMS AND METHODS Oct 7, 2024 Pending
Array ( [id] => 20123327 [patent_doc_number] => 20250238358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => METHOD OF OPERATING NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/908933 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18908933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/908933
METHOD OF OPERATING NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE Oct 7, 2024 Pending
Array ( [id] => 19726916 [patent_doc_number] => 20250029667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => PROGRAMMING MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/906735 [patent_app_country] => US [patent_app_date] => 2024-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18906735 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/906735
PROGRAMMING MEMORY DEVICES Oct 3, 2024 Pending
Array ( [id] => 20501656 [patent_doc_number] => 20260031118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => METHOD AND DEVICE FOR PARALLEL ANALOG IN-MEMORY COMPUTING [patent_app_type] => utility [patent_app_number] => 18/895326 [patent_app_country] => US [patent_app_date] => 2024-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18895326 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/895326
METHOD AND DEVICE FOR PARALLEL ANALOG IN-MEMORY COMPUTING Sep 23, 2024 Pending
Array ( [id] => 19696107 [patent_doc_number] => 20250014652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/888253 [patent_app_country] => US [patent_app_date] => 2024-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 535 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18888253 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/888253
SEMICONDUCTOR MEMORY DEVICE Sep 17, 2024 Pending
Array ( [id] => 19687727 [patent_doc_number] => 20250006272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/886210 [patent_app_country] => US [patent_app_date] => 2024-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18886210 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/886210
NONVOLATILE MEMORY DEVICE Sep 15, 2024 Pending
Array ( [id] => 19687708 [patent_doc_number] => 20250006253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => SYSTEMS, METHODS AND MEDIA OF OPTIMIZATION OF TEMPORARY READ ERRORS IN 3D NAND MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/830329 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830329 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/830329
SYSTEMS, METHODS AND MEDIA OF OPTIMIZATION OF TEMPORARY READ ERRORS IN 3D NAND MEMORY DEVICES Sep 9, 2024 Pending
Array ( [id] => 19574863 [patent_doc_number] => 20240379155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => NON-VOLATILE MEMORY BASED COMPUTE-IN-MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/783018 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783018 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783018
NON-VOLATILE MEMORY BASED COMPUTE-IN-MEMORY CELL Jul 23, 2024 Pending
Array ( [id] => 20002101 [patent_doc_number] => 20250140323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => LOGICAL BLOCK CONSTRUCTION FOR PHYSICAL BLOCKS COMPRISING MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING [patent_app_type] => utility [patent_app_number] => 18/781524 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781524 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781524
LOGICAL BLOCK CONSTRUCTION FOR PHYSICAL BLOCKS COMPRISING MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING Jul 22, 2024 Pending
Array ( [id] => 19574886 [patent_doc_number] => 20240379178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => GANGED SINGLE LEVEL CELL VERIFY IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/780167 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18780167 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/780167
GANGED SINGLE LEVEL CELL VERIFY IN A MEMORY DEVICE Jul 21, 2024 Pending
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