Search

Uyen Tran Smet

Examiner (ID: 5351, Phone: (571)272-2267 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
772
Issued Applications
671
Pending Applications
70
Abandoned Applications
42

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17708257 [patent_doc_number] => 20220208265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MEMORY DEVICE WITH ON-CHIP SACRIFICIAL MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/139059 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139059 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139059
Memory device with on-chip sacrificial memory cells Dec 30, 2020 Issued
Array ( [id] => 16781417 [patent_doc_number] => 20210118496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHOD FOR OPERATING A NON-VOLATILE MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/134471 [patent_app_country] => US [patent_app_date] => 2020-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134471 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134471
Method for operating a non-volatile memory cell Dec 26, 2020 Issued
Array ( [id] => 16752520 [patent_doc_number] => 20210104532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => MEMORY DEVICE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/125303 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125303 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125303
Memory device and forming method thereof Dec 16, 2020 Issued
Array ( [id] => 18796719 [patent_doc_number] => 11830545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Data programming techniques to store multiple bits of data per memory cell with high reliability [patent_app_type] => utility [patent_app_number] => 17/124380 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9803 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124380
Data programming techniques to store multiple bits of data per memory cell with high reliability Dec 15, 2020 Issued
Array ( [id] => 18463162 [patent_doc_number] => 11687452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Dynamic program-verify voltage adjustment for intra-block storage charge loss uniformity [patent_app_type] => utility [patent_app_number] => 17/123244 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123244 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123244
Dynamic program-verify voltage adjustment for intra-block storage charge loss uniformity Dec 15, 2020 Issued
Array ( [id] => 16731333 [patent_doc_number] => 20210098481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => MEMORY DEVICE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/120795 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120795 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120795
Memory device and forming method thereof Dec 13, 2020 Issued
Array ( [id] => 16781817 [patent_doc_number] => 20210118896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => MEMORY DEVICE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/115007 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115007
Memory device and forming method thereof Dec 7, 2020 Issued
Array ( [id] => 18415835 [patent_doc_number] => 11670380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Two-sided adjacent memory cell interference mitigation [patent_app_type] => utility [patent_app_number] => 17/114256 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 19163 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114256
Two-sided adjacent memory cell interference mitigation Dec 6, 2020 Issued
Array ( [id] => 16723520 [patent_doc_number] => 20210090667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => FUNCTIONAL SIGNAL LINE OVERDRIVE [patent_app_type] => utility [patent_app_number] => 17/113791 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113791 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113791
Functional signal line overdrive Dec 6, 2020 Issued
Array ( [id] => 19276475 [patent_doc_number] => 12026605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => FeFET unit cells for neuromorphic computing [patent_app_type] => utility [patent_app_number] => 17/110429 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/110429
FeFET unit cells for neuromorphic computing Dec 2, 2020 Issued
Array ( [id] => 17645023 [patent_doc_number] => 20220172762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => Ramp Write Techniques [patent_app_type] => utility [patent_app_number] => 17/107725 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107725
Ramp write techniques Nov 29, 2020 Issued
Array ( [id] => 17772171 [patent_doc_number] => 11404122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Sub-block size reduction for 3D non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/102430 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 13930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102430 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102430
Sub-block size reduction for 3D non-volatile memory Nov 22, 2020 Issued
Array ( [id] => 17925696 [patent_doc_number] => 11468956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/953755 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 15732 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953755 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953755
Memory device and method of operating the same Nov 19, 2020 Issued
Array ( [id] => 16973413 [patent_doc_number] => 11069392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Memory component with efficient write operations [patent_app_type] => utility [patent_app_number] => 17/099413 [patent_app_country] => US [patent_app_date] => 2020-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17099413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/099413
Memory component with efficient write operations Nov 15, 2020 Issued
Array ( [id] => 16943953 [patent_doc_number] => 11056201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Apparatus for determining data states of memory cells [patent_app_type] => utility [patent_app_number] => 17/095291 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 14969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095291
Apparatus for determining data states of memory cells Nov 10, 2020 Issued
Array ( [id] => 16631413 [patent_doc_number] => 20210050066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => MEMORY DEVICE AND AN OPERATING METHOD OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/085823 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085823
Memory device and an operating method of a memory device Oct 29, 2020 Issued
Array ( [id] => 16631402 [patent_doc_number] => 20210050055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => PAGE WRITES FOR TRIPLE LEVEL CELL FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 17/085362 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085362 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085362
Multi-level cell page writes Oct 29, 2020 Issued
Array ( [id] => 16624604 [patent_doc_number] => 20210043257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => MULTI-STEP RESET TECHNIQUE TO ENLARGE MEMORY WINDOW [patent_app_type] => utility [patent_app_number] => 17/082232 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082232 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/082232
Multi-step reset technique to enlarge memory window Oct 27, 2020 Issued
Array ( [id] => 17862647 [patent_doc_number] => 11443808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Semiconductor memory device and method of operating the semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/080262 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 14019 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/080262
Semiconductor memory device and method of operating the semiconductor memory device Oct 25, 2020 Issued
Array ( [id] => 16616979 [patent_doc_number] => 20210035632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => MEMORY ACCESS MODULE FOR PERFORMING A PLURALITY OF SENSING OPERATIONS TO GENERATE DIGITAL VALUES OF A STORAGE CELL IN ORDER TO PERFORM DECODING OF THE STORAGE CELL [patent_app_type] => utility [patent_app_number] => 17/075689 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075689
Memory access module for performing a plurality of sensing operations to generate digital values of a storage cell in order to perform decoding of the storage cell Oct 19, 2020 Issued
Menu