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Uyen Tran Smet

Examiner (ID: 12313, Phone: (571)272-2267 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
768
Issued Applications
665
Pending Applications
72
Abandoned Applications
42

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20488383 [patent_doc_number] => 20260024584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => HOLE PRE-CHARGE FROM BITLINE SIDE TO ENABLE FULL REVERSE ORDER PROGRAM SUB-BLOCK MODE [patent_app_type] => utility [patent_app_number] => 18/776359 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776359 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776359
HOLE PRE-CHARGE FROM BITLINE SIDE TO ENABLE FULL REVERSE ORDER PROGRAM SUB-BLOCK MODE Jul 17, 2024 Pending
Array ( [id] => 20000782 [patent_doc_number] => 20250139004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => DDR BUFFER DEVICE EQUALIZATION FOR SELF-TRAINING MODE [patent_app_type] => utility [patent_app_number] => 18/768716 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768716 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768716
DDR BUFFER DEVICE EQUALIZATION FOR SELF-TRAINING MODE Jul 9, 2024 Pending
Array ( [id] => 20461948 [patent_doc_number] => 20260011377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => ERASE METHOD FOR MEMORY DEVICE AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/762246 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762246
ERASE METHOD FOR MEMORY DEVICE AND MEMORY DEVICE Jul 1, 2024 Pending
Array ( [id] => 20124259 [patent_doc_number] => 20250239290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND SELF-REFRESH METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/758646 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758646 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758646
SEMICONDUCTOR MEMORY DEVICE AND SELF-REFRESH METHOD THEREOF Jun 27, 2024 Pending
Array ( [id] => 19661773 [patent_doc_number] => 20240428838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SYNAPSE DEVICE INCLUDING FERROELECTRIC FIELD EFFECT TRANSISTOR AND NEURAL NETWORK APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/748706 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748706 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748706
SYNAPSE DEVICE INCLUDING FERROELECTRIC FIELD EFFECT TRANSISTOR AND NEURAL NETWORK APPARATUS INCLUDING THE SAME Jun 19, 2024 Pending
Array ( [id] => 19500139 [patent_doc_number] => 20240339157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => CROSSBAR CIRCUITS FOR PERFORMING CONVOLUTION OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/749166 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749166 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749166
CROSSBAR CIRCUITS FOR PERFORMING CONVOLUTION OPERATIONS Jun 19, 2024 Pending
Array ( [id] => 19483738 [patent_doc_number] => 20240331780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => ADJUSTMENT OF PROGRAM VERIFY TARGETS CORRESPONDING TO A LAST PROGRAMMING DISTRIBUTION AND A PROGRAMMING DISTRIBUTION ADJACENT TO AN INITIAL PROGRAMMING DISTRIBUTION [patent_app_type] => utility [patent_app_number] => 18/738908 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738908
Adjustment of program verify targets corresponding to a last programming distribution and a programming distribution adjacent to an initial programming distribution Jun 9, 2024 Issued
Array ( [id] => 20806043 [patent_doc_number] => 12670955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Analog content addressable memory cell and array for soft decision boundaries and soft decision tree computation system using the same [patent_app_type] => utility [patent_app_number] => 18/733849 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 3036 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733849
ANALOG CONTENT ADDRESSABLE MEMORY CELL AND ARRAY FOR SOFT DECISION BOUNDARIES AND SOFT DECISION TREE COMPUTATION SYSTEM USING THE SAME Jun 4, 2024 Issued
Array ( [id] => 20791096 [patent_doc_number] => 12665012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Operation method of ferroelectric memory [patent_app_type] => utility [patent_app_number] => 18/674402 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674402 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674402
OPERATION METHOD OF FERROELECTRIC MEMORY May 23, 2024 Pending
Array ( [id] => 20196570 [patent_doc_number] => 20250273280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => MEMORY DEVICES, MEMORY SYSTEMS AND CONTROL METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/672925 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672925 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672925
MEMORY DEVICES, MEMORY SYSTEMS AND CONTROL METHODS THEREOF May 22, 2024 Pending
Array ( [id] => 19436779 [patent_doc_number] => 20240305277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/664387 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664387
Semiconductor integrated circuit May 14, 2024 Issued
Array ( [id] => 20367113 [patent_doc_number] => 20250356925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => NON-VOLATILE MEMORY WITH GROUPED BIT LINES FOR SENSING [patent_app_type] => utility [patent_app_number] => 18/663366 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663366 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663366
NON-VOLATILE MEMORY WITH GROUPED BIT LINES FOR SENSING May 13, 2024 Pending
Array ( [id] => 20338774 [patent_doc_number] => 20250342894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-06 [patent_title] => METHODS, DEVICES, AND SYSTEMS FOR ANOMALY DETECTION FOR NON-VOLATILE MEMORY DEVICE PROGRAMMING [patent_app_type] => utility [patent_app_number] => 18/653446 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653446 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653446
METHODS, DEVICES, AND SYSTEMS FOR ANOMALY DETECTION FOR NON-VOLATILE MEMORY DEVICE PROGRAMMING May 1, 2024 Pending
Array ( [id] => 19531500 [patent_doc_number] => 20240355402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => KNOWN-FAILURE ERROR HANDLING IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/637913 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637913 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637913
KNOWN-FAILURE ERROR HANDLING IN A MEMORY SUB-SYSTEM Apr 16, 2024 Pending
Array ( [id] => 20648181 [patent_doc_number] => 12603131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Gate-controlled thyristor and CAM array [patent_app_type] => utility [patent_app_number] => 18/636277 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 2697 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636277 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636277
Gate-controlled thyristor and CAM array Apr 15, 2024 Issued
Array ( [id] => 19603097 [patent_doc_number] => 20240393977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => PRE-PROGRAM PASS TO REDUCE SYSTEM BUFFER REQUIREMENT WHEN PROGRAMMING QUAD-LEVEL CELL (QLC) MEMORY [patent_app_type] => utility [patent_app_number] => 18/636584 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636584
PRE-PROGRAM PASS TO REDUCE SYSTEM BUFFER REQUIREMENT WHEN PROGRAMMING QUAD-LEVEL CELL (QLC) MEMORY Apr 15, 2024 Pending
Array ( [id] => 19321221 [patent_doc_number] => 20240242767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => STORAGE DEVICE FOR GENERATING IDENTITY CODE AND IDENTITY CODE GENERATING METHOD [patent_app_type] => utility [patent_app_number] => 18/623116 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623116 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623116
Storage device for generating identity code and identity code generating method Mar 31, 2024 Issued
Array ( [id] => 19483745 [patent_doc_number] => 20240331787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => START-UP CIRCUIT FOR BANDGAP REFERENCES IN A NAND FLASH [patent_app_type] => utility [patent_app_number] => 18/618456 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618456 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618456
START-UP CIRCUIT FOR BANDGAP REFERENCES IN A NAND FLASH Mar 26, 2024 Pending
Array ( [id] => 19515397 [patent_doc_number] => 20240347083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => TECHNIQUES TO MITIGATE MEMORY DIE MISALIGNMENT [patent_app_type] => utility [patent_app_number] => 18/614244 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614244
Techniques to mitigate memory die misalignment Mar 21, 2024 Issued
Array ( [id] => 19765696 [patent_doc_number] => 12223994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays [patent_app_type] => utility [patent_app_number] => 18/606333 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5873 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606333 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606333
Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays Mar 14, 2024 Issued
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