
Uyen Tran Smet
Examiner (ID: 5351, Phone: (571)272-2267 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 772 |
| Issued Applications | 671 |
| Pending Applications | 70 |
| Abandoned Applications | 42 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15077175
[patent_doc_number] => 10468082
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-11-05
[patent_title] => MRAM sense amplifier having a pre-amplifier with improved output offset cancellation
[patent_app_type] => utility
[patent_app_number] => 16/140417
[patent_app_country] => US
[patent_app_date] => 2018-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5225
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140417
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/140417 | MRAM sense amplifier having a pre-amplifier with improved output offset cancellation | Sep 23, 2018 | Issued |
Array
(
[id] => 17745435
[patent_doc_number] => 11393514
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-19
[patent_title] => Turbo mode SRAM for high performance
[patent_app_type] => utility
[patent_app_number] => 16/139779
[patent_app_country] => US
[patent_app_date] => 2018-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5652
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139779
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/139779 | Turbo mode SRAM for high performance | Sep 23, 2018 | Issued |
Array
(
[id] => 15984235
[patent_doc_number] => 10672452
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Temperature informed memory refresh
[patent_app_type] => utility
[patent_app_number] => 16/138115
[patent_app_country] => US
[patent_app_date] => 2018-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10220
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138115
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/138115 | Temperature informed memory refresh | Sep 20, 2018 | Issued |
Array
(
[id] => 15657263
[patent_doc_number] => 20200091162
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-19
[patent_title] => ONE TRANSISTOR AND ONE FERROELECTRIC CAPACITOR MEMORY CELLS IN DIAGONAL ARRANGEMENTS
[patent_app_type] => utility
[patent_app_number] => 16/132281
[patent_app_country] => US
[patent_app_date] => 2018-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22371
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132281
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/132281 | One transistor and one ferroelectric capacitor memory cells in diagonal arrangements | Sep 13, 2018 | Issued |
Array
(
[id] => 17731002
[patent_doc_number] => 11387404
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-12
[patent_title] => Magnetoelectric spin orbit logic based minority gate
[patent_app_type] => utility
[patent_app_number] => 16/130905
[patent_app_country] => US
[patent_app_date] => 2018-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 36
[patent_no_of_words] => 15929
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16130905
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/130905 | Magnetoelectric spin orbit logic based minority gate | Sep 12, 2018 | Issued |
Array
(
[id] => 13995319
[patent_doc_number] => 20190066817
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-28
[patent_title] => ERASE PAGE CHECK
[patent_app_type] => utility
[patent_app_number] => 16/129422
[patent_app_country] => US
[patent_app_date] => 2018-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11823
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16129422
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/129422 | Erase page check | Sep 11, 2018 | Issued |
Array
(
[id] => 13784919
[patent_doc_number] => 20190005998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => SEMICONDUCTOR STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/126685
[patent_app_country] => US
[patent_app_date] => 2018-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8820
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16126685
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/126685 | Semiconductor storage device | Sep 9, 2018 | Issued |
Array
(
[id] => 15474773
[patent_doc_number] => 10553269
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-04
[patent_title] => High-speed data transfer periods for thyristor memory cell arrays
[patent_app_type] => utility
[patent_app_number] => 16/124133
[patent_app_country] => US
[patent_app_date] => 2018-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 5012
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124133
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/124133 | High-speed data transfer periods for thyristor memory cell arrays | Sep 5, 2018 | Issued |
Array
(
[id] => 13782031
[patent_doc_number] => 20190004554
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => REGULATOR CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/122725
[patent_app_country] => US
[patent_app_date] => 2018-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7950
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16122725
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/122725 | Regulator circuit and semiconductor storage device | Sep 4, 2018 | Issued |
Array
(
[id] => 17106333
[patent_doc_number] => 11126550
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-09-21
[patent_title] => Integrating a resistive memory system into a multicore CPU die to achieve massive memory parallelism
[patent_app_type] => utility
[patent_app_number] => 16/121339
[patent_app_country] => US
[patent_app_date] => 2018-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 16010
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121339
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/121339 | Integrating a resistive memory system into a multicore CPU die to achieve massive memory parallelism | Sep 3, 2018 | Issued |
Array
(
[id] => 15563831
[patent_doc_number] => 20200066327
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-27
[patent_title] => MEMORY ARRAYS WITH VERTICAL THIN FILM TRANSISTORS COUPLED BETWEEN DIGIT LINES
[patent_app_type] => utility
[patent_app_number] => 16/110349
[patent_app_country] => US
[patent_app_date] => 2018-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5267
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16110349
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/110349 | Memory arrays with vertical thin film transistors coupled between digit lines | Aug 22, 2018 | Issued |
Array
(
[id] => 15563809
[patent_doc_number] => 20200066316
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-27
[patent_title] => MEMORY CIRCUIT AND METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/108326
[patent_app_country] => US
[patent_app_date] => 2018-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3143
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16108326
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/108326 | Memory circuit and method thereof | Aug 21, 2018 | Issued |
Array
(
[id] => 13613057
[patent_doc_number] => 20180358078
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => MEMORY CELL SENSING WITH STORAGE COMPONENT ISOLATION
[patent_app_type] => utility
[patent_app_number] => 16/107925
[patent_app_country] => US
[patent_app_date] => 2018-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10872
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107925
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/107925 | Memory cell sensing with storage component isolation | Aug 20, 2018 | Issued |
Array
(
[id] => 14644011
[patent_doc_number] => 10366753
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-30
[patent_title] => Correlated electron switch programmable fabric
[patent_app_type] => utility
[patent_app_number] => 15/999694
[patent_app_country] => US
[patent_app_date] => 2018-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 11539
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15999694
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/999694 | Correlated electron switch programmable fabric | Aug 19, 2018 | Issued |
Array
(
[id] => 13905809
[patent_doc_number] => 20190042109
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-07
[patent_title] => WEAR LEVELING
[patent_app_type] => utility
[patent_app_number] => 16/102807
[patent_app_country] => US
[patent_app_date] => 2018-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5902
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102807
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/102807 | Wear leveling | Aug 13, 2018 | Issued |
Array
(
[id] => 17195856
[patent_doc_number] => 11164621
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-02
[patent_title] => Sense amplifier, semiconductor device, operation method thereof, and electronic device
[patent_app_type] => utility
[patent_app_number] => 16/636366
[patent_app_country] => US
[patent_app_date] => 2018-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 35
[patent_no_of_words] => 36972
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16636366
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/636366 | Sense amplifier, semiconductor device, operation method thereof, and electronic device | Aug 8, 2018 | Issued |
Array
(
[id] => 13581521
[patent_doc_number] => 20180342309
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-29
[patent_title] => CALIBRATING I/O IMPEDANCES USING ESTIMATION OF MEMORY DIE TEMPERATURE
[patent_app_type] => utility
[patent_app_number] => 16/056682
[patent_app_country] => US
[patent_app_date] => 2018-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6167
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056682
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/056682 | Calibrating I/O impedances using estimation of memory die temperature | Aug 6, 2018 | Issued |
Array
(
[id] => 16609375
[patent_doc_number] => 10910390
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-02
[patent_title] => Memory device and forming method thereof
[patent_app_type] => utility
[patent_app_number] => 16/046042
[patent_app_country] => US
[patent_app_date] => 2018-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 27
[patent_no_of_words] => 11398
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046042
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/046042 | Memory device and forming method thereof | Jul 25, 2018 | Issued |
Array
(
[id] => 16034589
[patent_doc_number] => 10679721
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-09
[patent_title] => Structure and method for testing three-dimensional memory device
[patent_app_type] => utility
[patent_app_number] => 16/046869
[patent_app_country] => US
[patent_app_date] => 2018-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 10787
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046869
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/046869 | Structure and method for testing three-dimensional memory device | Jul 25, 2018 | Issued |
Array
(
[id] => 14952459
[patent_doc_number] => 10437493
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-08
[patent_title] => Storage device and data storing method thereof
[patent_app_type] => utility
[patent_app_number] => 16/029049
[patent_app_country] => US
[patent_app_date] => 2018-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3145
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029049
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/029049 | Storage device and data storing method thereof | Jul 5, 2018 | Issued |