Search

Uyen Tran Smet

Examiner (ID: 10372, Phone: (571)272-2267 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
744
Issued Applications
657
Pending Applications
59
Abandoned Applications
42

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19414503 [patent_doc_number] => 12080335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Signal sampling circuit and semiconductor memory [patent_app_type] => utility [patent_app_number] => 17/934185 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 19969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934185
Signal sampling circuit and semiconductor memory Sep 20, 2022 Issued
Array ( [id] => 20119753 [patent_doc_number] => 12369494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => MRAM top electrode structure with liner layer [patent_app_type] => utility [patent_app_number] => 17/932691 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932691 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932691
MRAM top electrode structure with liner layer Sep 15, 2022 Issued
Array ( [id] => 19037847 [patent_doc_number] => 20240087662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => MEMORY REPAIR SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/944691 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17944691 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/944691
Memory repair system and method Sep 13, 2022 Issued
Array ( [id] => 19906286 [patent_doc_number] => 12283298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Magnetoresistive random access memory with data scrubbing [patent_app_type] => utility [patent_app_number] => 17/931464 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17931464 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/931464
Magnetoresistive random access memory with data scrubbing Sep 11, 2022 Issued
Array ( [id] => 19022883 [patent_doc_number] => 20240079054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => INPUT/OUTPUT REFERENCE VOLTAGE TRAINING METHOD IN THREE-DIMENSIONAL MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/929450 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17929450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/929450
Input/output reference voltage training method in three-dimensional memory devices Sep 1, 2022 Issued
Array ( [id] => 18655267 [patent_doc_number] => 20230301118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/901485 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901485
Semiconductor memory device Aug 31, 2022 Issued
Array ( [id] => 20175736 [patent_doc_number] => 12394489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => In-place write techniques without erase in a memory device [patent_app_type] => utility [patent_app_number] => 17/897854 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 7374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/897854
In-place write techniques without erase in a memory device Aug 28, 2022 Issued
Array ( [id] => 18990865 [patent_doc_number] => 20240062834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => ADAPTIVE INTEGRITY SCAN IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/891852 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891852
Adaptive integrity scan in a memory sub-system Aug 18, 2022 Issued
Array ( [id] => 18061432 [patent_doc_number] => 20220392518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR FREQUENCY-DEPENDENT SIGNAL MODULATION [patent_app_type] => utility [patent_app_number] => 17/889154 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889154
Apparatuses, systems, and methods for frequency-dependent signal modulation Aug 15, 2022 Issued
Array ( [id] => 18061912 [patent_doc_number] => 20220392999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 17/889106 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889106 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889106
Semiconductor integrated circuit device Aug 15, 2022 Issued
Array ( [id] => 18819412 [patent_doc_number] => 20230393752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => VOLTAGE WINDOW ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/887244 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887244 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887244
VOLTAGE WINDOW ADJUSTMENT Aug 11, 2022 Pending
Array ( [id] => 20229149 [patent_doc_number] => 12417803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Neural network based method and device [patent_app_type] => utility [patent_app_number] => 17/883546 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10145 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883546 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883546
Neural network based method and device Aug 7, 2022 Issued
Array ( [id] => 19912374 [patent_doc_number] => 12288592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Performing sense operations in memory [patent_app_type] => utility [patent_app_number] => 17/873991 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873991
Performing sense operations in memory Jul 25, 2022 Issued
Array ( [id] => 18935242 [patent_doc_number] => 11887680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Reducing program verifies for multi-level NAND cells [patent_app_type] => utility [patent_app_number] => 17/873716 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873716
Reducing program verifies for multi-level NAND cells Jul 25, 2022 Issued
Array ( [id] => 18926777 [patent_doc_number] => 20240029781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => APPARATUSES AND METHODS FOR REPAIRING MUTLIPLE BIT LINES WITH A SAME COLUMN SELECT VALUE [patent_app_type] => utility [patent_app_number] => 17/813515 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813515 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813515
APPARATUSES AND METHODS FOR REPAIRING MUTLIPLE BIT LINES WITH A SAME COLUMN SELECT VALUE Jul 18, 2022 Pending
Array ( [id] => 18820841 [patent_doc_number] => 20230395182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => DIFFERENTIAL STROBE FAULT INDICATION [patent_app_type] => utility [patent_app_number] => 17/862082 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/862082
Differential strobe fault indication Jul 10, 2022 Issued
Array ( [id] => 18164077 [patent_doc_number] => 20230030672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => DIE-BASED HIGH AND LOW PRIORITY ERROR QUEUES [patent_app_type] => utility [patent_app_number] => 17/862006 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862006 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/862006
Die-based high and low priority error queues Jul 10, 2022 Issued
Array ( [id] => 18224646 [patent_doc_number] => 20230063640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => MEMORY SYSTEM PERFORMING PERFORMANCE ADJUSTING OPERATION [patent_app_type] => utility [patent_app_number] => 17/858374 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858374
Memory system performing performance adjusting operation Jul 5, 2022 Issued
Array ( [id] => 18224646 [patent_doc_number] => 20230063640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => MEMORY SYSTEM PERFORMING PERFORMANCE ADJUSTING OPERATION [patent_app_type] => utility [patent_app_number] => 17/858374 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858374
Memory system performing performance adjusting operation Jul 5, 2022 Issued
Array ( [id] => 18224646 [patent_doc_number] => 20230063640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => MEMORY SYSTEM PERFORMING PERFORMANCE ADJUSTING OPERATION [patent_app_type] => utility [patent_app_number] => 17/858374 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858374
Memory system performing performance adjusting operation Jul 5, 2022 Issued
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