Search

Uyen Tran Smet

Examiner (ID: 12313, Phone: (571)272-2267 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
768
Issued Applications
665
Pending Applications
72
Abandoned Applications
42

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20132081 [patent_doc_number] => 12374398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Forming operation of resistive memory device [patent_app_type] => utility [patent_app_number] => 18/457377 [patent_app_country] => US [patent_app_date] => 2023-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18457377 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/457377
Forming operation of resistive memory device Aug 28, 2023 Issued
Array ( [id] => 19531475 [patent_doc_number] => 20240355377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => MEMORY DEVICE FOR SELF-SEARCHING FOR BOUNDARY WORD LINE, METHOD FOR OPERATING MEMORY DEVICE, AND MEMORY SYSTEM INCLUDING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/455625 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455625 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/455625
MEMORY DEVICE FOR SELF-SEARCHING FOR BOUNDARY WORD LINE, METHOD FOR OPERATING MEMORY DEVICE, AND MEMORY SYSTEM INCLUDING MEMORY DEVICE Aug 24, 2023 Pending
Array ( [id] => 18820837 [patent_doc_number] => 20230395178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => CONTROLLING MEMORY INCLUDING MANAGING A CORRECTION VALUE TABLE [patent_app_type] => utility [patent_app_number] => 18/453567 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453567 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/453567
Controlling memory including managing a correction value table Aug 21, 2023 Issued
Array ( [id] => 18820797 [patent_doc_number] => 20230395138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => Systems and Methods for Reducing Standby Power in Floating Body Memory Devices [patent_app_type] => utility [patent_app_number] => 18/235478 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235478 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/235478
Systems and Methods for Reducing Standby Power in Floating Body Memory Devices Aug 17, 2023 Pending
Array ( [id] => 20203963 [patent_doc_number] => 12406746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Semiconductor storage apparatus capable of efficiently performing screening test [patent_app_type] => utility [patent_app_number] => 18/451113 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 1193 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451113
Semiconductor storage apparatus capable of efficiently performing screening test Aug 16, 2023 Issued
Array ( [id] => 20758850 [patent_doc_number] => 12651627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Peripheral structure arrangements of memory devices and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/234333 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 6758 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234333 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/234333
Peripheral structure arrangements of memory devices and methods for forming the same Aug 14, 2023 Issued
Array ( [id] => 19687699 [patent_doc_number] => 20250006244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => ASYMMETRIC PASS VOLTAGE SCHEME FOR NON-VOLATILE MEMORY APPARATUS SIZE REDUCTION [patent_app_type] => utility [patent_app_number] => 18/233640 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18233640 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/233640
ASYMMETRIC PASS VOLTAGE SCHEME FOR NON-VOLATILE MEMORY APPARATUS SIZE REDUCTION Aug 13, 2023 Pending
Array ( [id] => 19773110 [patent_doc_number] => 20250054536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/448479 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448479 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448479
Memory device adjusting reference voltage signal Aug 10, 2023 Issued
Array ( [id] => 19191173 [patent_doc_number] => 20240170086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => METHOD FOR OPERATING A MEMORY DEVICE AND MEMORY DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 18/360530 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360530
Method for operating a memory device and memory device thereof Jul 26, 2023 Issued
Array ( [id] => 19269078 [patent_doc_number] => 20240212782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY CONTROLLER, AN OPERATION METHOD THEREOF, A MEMORY DEVICE, AND A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/226340 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226340
MEMORY CONTROLLER, AN OPERATION METHOD THEREOF, A MEMORY DEVICE, AND A MEMORY SYSTEM Jul 25, 2023 Pending
Array ( [id] => 20667392 [patent_doc_number] => 12609172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Non-volatile memory with intelligent erase testing to avoid neighbor plane disturb [patent_app_type] => utility [patent_app_number] => 18/358651 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 18452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358651 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358651
Non-volatile memory with intelligent erase testing to avoid neighbor plane disturb Jul 24, 2023 Issued
Array ( [id] => 18865625 [patent_doc_number] => 20230420062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/357883 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357883 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357883
MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD THEREOF Jul 23, 2023 Pending
Array ( [id] => 19221239 [patent_doc_number] => 20240185943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => BINARY SEARCH BIT ERROR RATE ESTIMATION SCAN FOR NON-VOLATILE MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/219387 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/219387
BINARY SEARCH BIT ERROR RATE ESTIMATION SCAN FOR NON-VOLATILE MEMORY APPARATUS Jul 6, 2023 Pending
Array ( [id] => 20118217 [patent_doc_number] => 12367932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Memory device in which latch is coupled to source line and method of operation [patent_app_type] => utility [patent_app_number] => 18/218415 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218415 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/218415
Memory device in which latch is coupled to source line and method of operation Jul 4, 2023 Issued
Array ( [id] => 20482651 [patent_doc_number] => 12531127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Compact CAM array for decision tree inference (tree-CAM) [patent_app_type] => utility [patent_app_number] => 18/347318 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347318
Compact CAM array for decision tree inference (tree-CAM) Jul 4, 2023 Issued
Array ( [id] => 19363941 [patent_doc_number] => 20240265975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => NAND FLASH MEMORY DEVICE WITH ENHANCED DATA RETENTION CHARACTERISTICS AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/340473 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/340473
NAND flash memory device with enhanced data retention characteristics and operating method thereof Jun 22, 2023 Issued
Array ( [id] => 19384320 [patent_doc_number] => 20240274190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => MEMORY CIRCUIT AND METHOD OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 18/337267 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337267 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337267
MEMORY CIRCUIT AND METHOD OF OPERATING SAME Jun 18, 2023 Pending
Array ( [id] => 20375080 [patent_doc_number] => 12482522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Memory device and operating method of the memory device for reducing power consumption for program operation [patent_app_type] => utility [patent_app_number] => 18/337275 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4996 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337275
Memory device and operating method of the memory device for reducing power consumption for program operation Jun 18, 2023 Issued
Array ( [id] => 20538562 [patent_doc_number] => 12555641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Memory device for performing a program operation based on operation stage and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/333366 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3711 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333366 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333366
Memory device for performing a program operation based on operation stage and operating method thereof Jun 11, 2023 Issued
Array ( [id] => 19010256 [patent_doc_number] => 20240074327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MAGNETIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/332759 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332759
Magnetic memory device and method for manufacturing the same Jun 11, 2023 Issued
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