Search

Uyen Tran Smet

Examiner (ID: 12313, Phone: (571)272-2267 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
768
Issued Applications
665
Pending Applications
72
Abandoned Applications
42

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18661049 [patent_doc_number] => 20230307062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, CONTROLLER FOR CONTROLLING THE SAME, AND STORAGE DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/326606 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326606 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/326606
NON-VOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, CONTROLLER FOR CONTROLLING THE SAME, AND STORAGE DEVICE INCLUDING THE SAME May 30, 2023 Abandoned
Array ( [id] => 19596798 [patent_doc_number] => 12154651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Memory device, method of operating the memory device, memory module, and method of operating the memory module [patent_app_type] => utility [patent_app_number] => 18/201880 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 32 [patent_no_of_words] => 11402 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201880
Memory device, method of operating the memory device, memory module, and method of operating the memory module May 24, 2023 Issued
Array ( [id] => 19604413 [patent_doc_number] => 20240395293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => CONTENTION-FREE DUAL-VOLTAGE LOGIC CELL [patent_app_type] => utility [patent_app_number] => 18/323997 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323997
Contention-free dual-voltage logic cell May 24, 2023 Issued
Array ( [id] => 20495160 [patent_doc_number] => 12537036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Storage device, non-volatile memory device, and method of operating the non- volatile memory device to monitor repeated data patterns [patent_app_type] => utility [patent_app_number] => 18/322725 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322725 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322725
Storage device, non-volatile memory device, and method of operating the non- volatile memory device to monitor repeated data patterns May 23, 2023 Issued
Array ( [id] => 19605670 [patent_doc_number] => 20240396550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => DRIVER CIRCUITRY WITH REDUCED INTERSYMBOL INTERFERENCE JITTER [patent_app_type] => utility [patent_app_number] => 18/200432 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200432
Driver circuitry with reduced intersymbol interference jitter May 21, 2023 Issued
Array ( [id] => 18585740 [patent_doc_number] => 20230268004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SETTING LEVELS FOR A PROGRAMMING OPERATION IN A NEURAL NETWORK ARRAY [patent_app_type] => utility [patent_app_number] => 18/140103 [patent_app_country] => US [patent_app_date] => 2023-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18140103 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/140103
Setting levels for a programming operation in a neural network array Apr 26, 2023 Issued
Array ( [id] => 19356715 [patent_doc_number] => 12057170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Neural network array comprising one or more coarse cells and one or more fine cells [patent_app_type] => utility [patent_app_number] => 18/139908 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 57 [patent_no_of_words] => 17276 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139908 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/139908
Neural network array comprising one or more coarse cells and one or more fine cells Apr 25, 2023 Issued
Array ( [id] => 19261457 [patent_doc_number] => 12021530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Semiconductor integrated circuit [patent_app_type] => utility [patent_app_number] => 18/136924 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 94 [patent_no_of_words] => 27799 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18136924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/136924
Semiconductor integrated circuit Apr 19, 2023 Issued
Array ( [id] => 20441341 [patent_doc_number] => 12512181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Memory device performing target refresh operation and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/295851 [patent_app_country] => US [patent_app_date] => 2023-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6864 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295851 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295851
Memory device performing target refresh operation and operating method thereof Apr 4, 2023 Issued
Array ( [id] => 19175865 [patent_doc_number] => 20240161839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/193474 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193474 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/193474
MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION AND METHOD OF OPERATING THE SAME Mar 29, 2023 Pending
Array ( [id] => 20581205 [patent_doc_number] => 12573459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Semiconductor storage device having depletion-type memory cell transistors [patent_app_type] => utility [patent_app_number] => 18/177115 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2468 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177115
Semiconductor storage device having depletion-type memory cell transistors Mar 1, 2023 Issued
Array ( [id] => 20581211 [patent_doc_number] => 12573465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Error correction code circuit and semiconductor apparatus including the error correction code circuit [patent_app_type] => utility [patent_app_number] => 18/104907 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 1040 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104907 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104907
Error correction code circuit and semiconductor apparatus including the error correction code circuit Feb 1, 2023 Issued
Array ( [id] => 19835486 [patent_doc_number] => 20250087272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => METHOD FOR OPERATING FERROELECTRIC-BASED THREE-DIMENSIONAL FLASH MEMORY INCLUDING DATA STORAGE PATTERN [patent_app_type] => utility [patent_app_number] => 18/725991 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18725991 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/725991
METHOD FOR OPERATING FERROELECTRIC-BASED THREE-DIMENSIONAL FLASH MEMORY INCLUDING DATA STORAGE PATTERN Jan 19, 2023 Pending
Array ( [id] => 18455850 [patent_doc_number] => 20230197131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => ELECTRONIC DEVICE, METHOD FOR CONTROLLING STORING OPERATION, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/067679 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067679 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067679
Electronic device, method for controlling storing operation, and storage medium Dec 15, 2022 Issued
Array ( [id] => 18439692 [patent_doc_number] => 20230186987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SELECTOR RESISTIVE MEMORY, EQUIPPED WITH A CAPACITOR WRITING, AND ASSOCIATED WRITING METHOD [patent_app_type] => utility [patent_app_number] => 18/079325 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18079325 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/079325
Resistive memory with selector, equipped with a write capacitor, and associated writing method Dec 11, 2022 Issued
Array ( [id] => 19773133 [patent_doc_number] => 20250054559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/718810 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18718810 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/718810
SEMICONDUCTOR STORAGE DEVICE AND METHOD Dec 1, 2022 Pending
Array ( [id] => 18255375 [patent_doc_number] => 20230082414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/057386 [patent_app_country] => US [patent_app_date] => 2022-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18057386 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/057386
Nonvolatile memory device and storage device including nonvolatile memory device Nov 20, 2022 Issued
Array ( [id] => 19539245 [patent_doc_number] => 12131800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Physically unclonable cell using dual-interlocking and error correction techniques [patent_app_type] => utility [patent_app_number] => 18/056158 [patent_app_country] => US [patent_app_date] => 2022-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3497 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18056158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/056158
Physically unclonable cell using dual-interlocking and error correction techniques Nov 15, 2022 Issued
Array ( [id] => 18408680 [patent_doc_number] => 20230170033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => PROGRAM VERIFY PAIRING IN A MULTI-LEVEL CELL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/987780 [patent_app_country] => US [patent_app_date] => 2022-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17987780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/987780
PROGRAM VERIFY PAIRING IN A MULTI-LEVEL CELL MEMORY DEVICE Nov 14, 2022 Pending
Array ( [id] => 19858041 [patent_doc_number] => 12260891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => MFMFET, MFMFET array, and the operating method thereof [patent_app_type] => utility [patent_app_number] => 17/982156 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4630 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982156
MFMFET, MFMFET array, and the operating method thereof Nov 6, 2022 Issued
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