Search

Valentin Neacsu

Examiner (ID: 12324, Phone: (571)272-6265 , Office: P/3721 )

Most Active Art Unit
3731
Art Unit(s)
3721, 3611, 3731
Total Applications
424
Issued Applications
324
Pending Applications
4
Abandoned Applications
104

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6831022 [patent_doc_number] => 20030182080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Counter system and method' [patent_app_type] => new [patent_app_number] => 10/106536 [patent_app_country] => US [patent_app_date] => 2002-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3288 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20030182080.pdf [firstpage_image] =>[orig_patent_app_number] => 10106536 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/106536
Counter system and method Mar 24, 2002 Issued
Array ( [id] => 5990601 [patent_doc_number] => 20020099883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Overflow detector for FIFO' [patent_app_type] => new [patent_app_number] => 10/104870 [patent_app_country] => US [patent_app_date] => 2002-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2467 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099883.pdf [firstpage_image] =>[orig_patent_app_number] => 10104870 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/104870
Overflow detector for FIFO Mar 20, 2002 Issued
Array ( [id] => 1360182 [patent_doc_number] => 06580776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-17 [patent_title] => 'Glitch-free frequency dividing circuit' [patent_app_type] => B2 [patent_app_number] => 10/093289 [patent_app_country] => US [patent_app_date] => 2002-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3767 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/580/06580776.pdf [firstpage_image] =>[orig_patent_app_number] => 10093289 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/093289
Glitch-free frequency dividing circuit Mar 4, 2002 Issued
Array ( [id] => 6154706 [patent_doc_number] => 20020145458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Clock-skew resistant chain of sequential cells' [patent_app_type] => new [patent_app_number] => 10/086851 [patent_app_country] => US [patent_app_date] => 2002-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3755 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145458.pdf [firstpage_image] =>[orig_patent_app_number] => 10086851 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/086851
Clock-skew resistant chain of sequential cells Feb 28, 2002 Abandoned
Array ( [id] => 7279163 [patent_doc_number] => 20040061540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Clock reproduction circuit' [patent_app_type] => new [patent_app_number] => 10/467747 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3393 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061540.pdf [firstpage_image] =>[orig_patent_app_number] => 10467747 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/467747
Clock reproduction circuit Feb 24, 2002 Issued
Array ( [id] => 1316292 [patent_doc_number] => 06618462 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Digital frequency divider' [patent_app_type] => B1 [patent_app_number] => 10/077114 [patent_app_country] => US [patent_app_date] => 2002-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8921 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618462.pdf [firstpage_image] =>[orig_patent_app_number] => 10077114 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/077114
Digital frequency divider Feb 14, 2002 Issued
Array ( [id] => 6705454 [patent_doc_number] => 20030152188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'System and method for automatic generation of an at-speed counter' [patent_app_type] => new [patent_app_number] => 10/071506 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3686 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20030152188.pdf [firstpage_image] =>[orig_patent_app_number] => 10071506 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/071506
System and method for automatic generation of an at-speed counter Feb 7, 2002 Issued
Array ( [id] => 1442996 [patent_doc_number] => 06496556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Step-down clock control and method for improving convergence for a digitally controlled self-calibrating VCO' [patent_app_type] => B1 [patent_app_number] => 10/047189 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3130 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496556.pdf [firstpage_image] =>[orig_patent_app_number] => 10047189 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/047189
Step-down clock control and method for improving convergence for a digitally controlled self-calibrating VCO Jan 14, 2002 Issued
Array ( [id] => 7631970 [patent_doc_number] => 06665367 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Embedded frequency counter with flexible configuration' [patent_app_type] => B1 [patent_app_number] => 10/034455 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6741 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665367.pdf [firstpage_image] =>[orig_patent_app_number] => 10034455 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034455
Embedded frequency counter with flexible configuration Dec 26, 2001 Issued
Array ( [id] => 1096036 [patent_doc_number] => 06826250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Clock divider with error detection and reset capabilities' [patent_app_type] => B2 [patent_app_number] => 10/028047 [patent_app_country] => US [patent_app_date] => 2001-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826250.pdf [firstpage_image] =>[orig_patent_app_number] => 10028047 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/028047
Clock divider with error detection and reset capabilities Dec 18, 2001 Issued
Array ( [id] => 6670512 [patent_doc_number] => 20030115497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'System for maintaining the stability of a programmable frequency multiplier' [patent_app_type] => new [patent_app_number] => 10/017618 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2437 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20030115497.pdf [firstpage_image] =>[orig_patent_app_number] => 10017618 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017618
System for maintaining the stability of a programmable frequency multiplier Dec 13, 2001 Issued
Array ( [id] => 6304504 [patent_doc_number] => 20020094057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Shift register' [patent_app_type] => new [patent_app_number] => 10/017246 [patent_app_country] => US [patent_app_date] => 2001-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2207 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094057.pdf [firstpage_image] =>[orig_patent_app_number] => 10017246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017246
Shift register Dec 12, 2001 Abandoned
Array ( [id] => 1292839 [patent_doc_number] => 06639963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-28 [patent_title] => 'Up/down gray code counter and solid-state image sensor provided with such a counter' [patent_app_type] => B2 [patent_app_number] => 10/005082 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7398 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639963.pdf [firstpage_image] =>[orig_patent_app_number] => 10005082 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005082
Up/down gray code counter and solid-state image sensor provided with such a counter Dec 6, 2001 Issued
09/979968 Method of counting security documents Nov 27, 2001 Abandoned
Array ( [id] => 1594093 [patent_doc_number] => 06483887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => 'Timer control circuit' [patent_app_type] => B2 [patent_app_number] => 09/992428 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4393 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483887.pdf [firstpage_image] =>[orig_patent_app_number] => 09992428 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992428
Timer control circuit Nov 25, 2001 Issued
Array ( [id] => 6127038 [patent_doc_number] => 20020075989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'High-speed counter with sequential binary count order and method thereof' [patent_app_type] => new [patent_app_number] => 09/994491 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4079 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20020075989.pdf [firstpage_image] =>[orig_patent_app_number] => 09994491 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994491
High-speed counter with sequential binary count order and method thereof Nov 25, 2001 Abandoned
Array ( [id] => 6580008 [patent_doc_number] => 20020041198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Area efficient redundancy multiplexer circuit technique for integrated circuit devices providing significantly reduced parasitic capacitance' [patent_app_type] => new [patent_app_number] => 10/010336 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20020041198.pdf [firstpage_image] =>[orig_patent_app_number] => 10010336 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010336
Area efficient redundancy multiplexer circuit technique for integrated circuit devices providing significantly reduced parasitic capacitance Nov 12, 2001 Issued
Array ( [id] => 1311748 [patent_doc_number] => 06621886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Shift register having fewer lines therein, and liquid crystal display having the same' [patent_app_type] => B2 [patent_app_number] => 10/038181 [patent_app_country] => US [patent_app_date] => 2001-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621886.pdf [firstpage_image] =>[orig_patent_app_number] => 10038181 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038181
Shift register having fewer lines therein, and liquid crystal display having the same Oct 22, 2001 Issued
Array ( [id] => 1594097 [patent_doc_number] => 06483888 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Clock divider with bypass and stop clock' [patent_app_type] => B1 [patent_app_number] => 09/974987 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2639 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483888.pdf [firstpage_image] =>[orig_patent_app_number] => 09974987 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/974987
Clock divider with bypass and stop clock Oct 10, 2001 Issued
Array ( [id] => 1578815 [patent_doc_number] => 06470064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Extended length counter chains in FPGA logic' [patent_app_type] => B2 [patent_app_number] => 09/973147 [patent_app_country] => US [patent_app_date] => 2001-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1044 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470064.pdf [firstpage_image] =>[orig_patent_app_number] => 09973147 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973147
Extended length counter chains in FPGA logic Oct 7, 2001 Issued
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