Search

Valerie N. Newton

Examiner (ID: 2467, Phone: (571)270-5015 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2829, 2823, 4122
Total Applications
1018
Issued Applications
802
Pending Applications
97
Abandoned Applications
153

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14252625 [patent_doc_number] => 10276519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Package substrate differential impedance optimization for 25 to 60 Gbps and beyond [patent_app_type] => utility [patent_app_number] => 15/495881 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 70 [patent_no_of_words] => 15557 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 659 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15495881 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/495881
Package substrate differential impedance optimization for 25 to 60 Gbps and beyond Apr 23, 2017 Issued
Array ( [id] => 16293765 [patent_doc_number] => 10770621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Semiconductor wafer [patent_app_type] => utility [patent_app_number] => 16/092007 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7680 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16092007 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/092007
Semiconductor wafer Apr 6, 2017 Issued
Array ( [id] => 14382625 [patent_doc_number] => 20190165225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => COMPONENT HAVING A REFLECTOR AND METHOD OF PRODUCING COMPONENTS [patent_app_type] => utility [patent_app_number] => 16/092026 [patent_app_country] => US [patent_app_date] => 2017-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16092026 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/092026
Component having a reflector and method of producing components Apr 5, 2017 Issued
Array ( [id] => 13159583 [patent_doc_number] => 10096525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Method for fabricating self-aligned contact in a semiconductor device [patent_app_type] => utility [patent_app_number] => 15/479418 [patent_app_country] => US [patent_app_date] => 2017-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 33 [patent_no_of_words] => 7166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479418 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/479418
Method for fabricating self-aligned contact in a semiconductor device Apr 4, 2017 Issued
Array ( [id] => 11760433 [patent_doc_number] => 20170207303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'SEMICONDUCTOR MULTILAYER STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/477598 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3078 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477598 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477598
SEMICONDUCTOR MULTILAYER STRUCTURE Apr 2, 2017 Abandoned
Array ( [id] => 11760212 [patent_doc_number] => 20170207081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'LITHOGRAPHIC TECHNIQUE FOR FEATURE CUT BY LINE-END SHRINK' [patent_app_type] => utility [patent_app_number] => 15/477588 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477588 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477588
Lithographic technique for feature cut by line-end shrink Apr 2, 2017 Issued
Array ( [id] => 17941726 [patent_doc_number] => 11476185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Innovative way to design silicon to overcome reticle limit [patent_app_type] => utility [patent_app_number] => 16/481421 [patent_app_country] => US [patent_app_date] => 2017-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5573 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16481421 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/481421
Innovative way to design silicon to overcome reticle limit Mar 31, 2017 Issued
Array ( [id] => 15300073 [patent_doc_number] => 20190393172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => RFIC HAVING COAXIAL INTERCONNECT AND MOLDED LAYER [patent_app_type] => utility [patent_app_number] => 16/481392 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16481392 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/481392
RFIC having coaxial interconnect and molded layer Mar 29, 2017 Issued
Array ( [id] => 16835217 [patent_doc_number] => 11011477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => High-reliability electronic packaging structure, circuit board, and device [patent_app_type] => utility [patent_app_number] => 16/339195 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 19 [patent_no_of_words] => 4670 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16339195 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/339195
High-reliability electronic packaging structure, circuit board, and device Mar 29, 2017 Issued
Array ( [id] => 15969635 [patent_doc_number] => 20200168569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => SEMICONDUCTOR PACKAGE HAVING A COAXIAL FIRST LAYER INTERCONNECT [patent_app_type] => utility [patent_app_number] => 16/481385 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16481385 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/481385
Semiconductor package having a coaxial first layer interconnect Mar 29, 2017 Issued
Array ( [id] => 15299947 [patent_doc_number] => 20190393109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => PACKAGE SUBSTRATE HAVING POLYMER-DERIVED CERAMIC CORE [patent_app_type] => utility [patent_app_number] => 16/481216 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16481216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/481216
Package substrate having polymer-derived ceramic core Mar 29, 2017 Issued
Array ( [id] => 16746690 [patent_doc_number] => 10971695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Multilayer reflection electrode film, multilayer reflection electrode pattern, and method of forming multilayer reflection electrode pattern [patent_app_type] => utility [patent_app_number] => 16/086623 [patent_app_country] => US [patent_app_date] => 2017-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 11863 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16086623 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/086623
Multilayer reflection electrode film, multilayer reflection electrode pattern, and method of forming multilayer reflection electrode pattern Mar 21, 2017 Issued
Array ( [id] => 12314268 [patent_doc_number] => 09941141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Guard ring structure of semiconductor arrangement [patent_app_type] => utility [patent_app_number] => 15/463213 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463213 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463213
Guard ring structure of semiconductor arrangement Mar 19, 2017 Issued
Array ( [id] => 13145749 [patent_doc_number] => 10090213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Interposer test structures and methods [patent_app_type] => utility [patent_app_number] => 15/449683 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 66 [patent_no_of_words] => 13523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449683 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/449683
Interposer test structures and methods Mar 2, 2017 Issued
Array ( [id] => 11710587 [patent_doc_number] => 20170179086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'LIGHT-EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 15/443605 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 6812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443605 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443605
Light-emitting device Feb 26, 2017 Issued
Array ( [id] => 13613847 [patent_doc_number] => 20180358473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => THIN-FILM TRANSISTOR (TFT) AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/558104 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15558104 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/558104
Thin-film transistor (TFT) and manufacturing method thereof, array substrate and manufacturing method thereof, and display device Feb 23, 2017 Issued
Array ( [id] => 11710884 [patent_doc_number] => 20170179383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'METHOD AND APPARATUS PROVIDING MULTI-PLANED ARRAY MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/437308 [patent_app_country] => US [patent_app_date] => 2017-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7790 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/437308
Method and apparatus providing multi-planed array memory device Feb 19, 2017 Issued
Array ( [id] => 11666100 [patent_doc_number] => 20170154819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'SYSTEMS AND METHODS FOR CONTROLLING RELEASE OF TRANSFERABLE SEMICONDUCTOR STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/430101 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13173 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430101 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/430101
Systems and methods for controlling release of transferable semiconductor structures Feb 9, 2017 Issued
Array ( [id] => 15889733 [patent_doc_number] => 10651222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Solid-state imaging device and electronic apparatus [patent_app_type] => utility [patent_app_number] => 16/084602 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16084602 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/084602
Solid-state imaging device and electronic apparatus Jan 17, 2017 Issued
Array ( [id] => 12936361 [patent_doc_number] => 09831352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Semiconductor device and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 15/400077 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 31 [patent_no_of_words] => 12037 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400077 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/400077
Semiconductor device and method for manufacturing same Jan 5, 2017 Issued
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