Valerie N. Newton

Array ( [id] => 10943534 [patent_doc_number] => 20140346555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'Sealed Thin-Film Device as well as Method of Repairing, System for Repairing and Computer Program Product' [patent_app_type] => utility [patent_app_number] => 14/360563 [patent_app_country] => US [patent_app_date] => 2012-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15118 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14360563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8668969 [patent_doc_number] => 20130043507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'Semiconductor Device with a Buried Stressor' [patent_app_type] => utility [patent_app_number] => 13/658348 [patent_app_country] => US [patent_app_date] => 2012-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4391 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9648465 [patent_doc_number] => 08802476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Semiconductor thermocouple and sensor' [patent_app_type] => utility [patent_app_number] => 13/654591 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 4689 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8606667 [patent_doc_number] => 20130011979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'SELF-ALIGNED SEMICONDUCTOR DEVICES WITH REDUCED GATE-SOURCE LEAKAGE UNDER REVERSE BIAS AND METHODS OF MAKING' [patent_app_type] => utility [patent_app_number] => 13/613453 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3219 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13613453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8634852 [patent_doc_number] => 20130026655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'CHIP PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/438103 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5943 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10035453 [patent_doc_number] => 09076779 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-07 [patent_title] => 'Packaging of electronic circuitry' [patent_app_type] => utility [patent_app_number] => 13/438707 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 6383 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8901364 [patent_doc_number] => 20130168867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'METHOD FOR FORMING METAL LINE IN SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/438648 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2655 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9589953 [patent_doc_number] => 08779497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Electrical erasable programmable read-only memory and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/438678 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3470 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9971716 [patent_doc_number] => 09018730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Microstructure device comprising a face to face electromagnetic near field coupling between stacked device portions and method of forming the device' [patent_app_type] => utility [patent_app_number] => 13/438684 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 32 [patent_no_of_words] => 12963 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9064925 [patent_doc_number] => 20130256681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'GROUP III NITRIDE-BASED HIGH ELECTRON MOBILITY TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/437091 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1986 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8913905 [patent_doc_number] => 20130175531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/437003 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4261 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9575871 [patent_doc_number] => 08766288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Display panel and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/436994 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4404 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13436994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9064903 [patent_doc_number] => 20130256659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'REDUCTION OF OCD MEASUREMENT NOISE BY WAY OF METAL VIA SLOTS' [patent_app_type] => utility [patent_app_number] => 13/436952 [patent_app_country] => US [patent_app_date] => 2012-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13436952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9065004 [patent_doc_number] => 20130256760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'METHOD FOR FORMING GROUP III/V CONFORMAL LAYERS ON SILICON SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 13/436644 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13436644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9300217 [patent_doc_number] => 08648448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Semiconductor device and method of shielding semiconductor die from inter-device interference' [patent_app_type] => utility [patent_app_number] => 13/339185 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 7767 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13339185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8274856 [patent_doc_number] => 20120168728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'Organic Electronic Devices Prepared Using Decomposable Polymer Additives' [patent_app_type] => utility [patent_app_number] => 13/333547 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6960 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8133951 [patent_doc_number] => 20120091527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 13/331230 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6408 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20120091527.pdf [firstpage_image] =>[orig_patent_app_number] => 13331230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7784305 [patent_doc_number] => 20120045861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/285278 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16241 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20120045861.pdf [firstpage_image] =>[orig_patent_app_number] => 13285278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8960835 [patent_doc_number] => 20130200437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'METHOD OF FORMING NANOGAP PATTERN, BIOSENSOR HAVING THE NANOGAP PATTERN, AND METHOD OF MANUFACTURING THE BIOSENSOR' [patent_app_type] => utility [patent_app_number] => 13/824367 [patent_app_country] => US [patent_app_date] => 2011-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5734 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13824367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11770255 [patent_doc_number] => 09378947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'Buffer layer deposition for thin-film solar cells' [patent_app_type] => utility [patent_app_number] => 13/273013 [patent_app_country] => US [patent_app_date] => 2011-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9542 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13273013 [rel_patent_id] =>[rel_patent_doc_number] =>)