Search

Valerie N. Newton

Examiner (ID: 2467, Phone: (571)270-5015 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2829, 2823, 4122
Total Applications
1018
Issued Applications
802
Pending Applications
97
Abandoned Applications
153

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19414930 [patent_doc_number] => 12080769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Contact structure with silicide and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/672098 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 6666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672098 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/672098
Contact structure with silicide and method for forming the same Feb 14, 2022 Issued
Array ( [id] => 17615327 [patent_doc_number] => 20220157607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => Method for Annealing a Gate Insulation Layer on a Wide Band Gap Semiconductor Substrate [patent_app_type] => utility [patent_app_number] => 17/666654 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/666654
Method for annealing a gate insulation layer on a wide band gap semiconductor substrate Feb 7, 2022 Issued
Array ( [id] => 19858206 [patent_doc_number] => 12261057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias [patent_app_type] => utility [patent_app_number] => 17/592442 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 10175 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17592442 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/592442
Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias Feb 2, 2022 Issued
Array ( [id] => 17599753 [patent_doc_number] => 20220149327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => DISPLAY APPARATUS, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/581783 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581783 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581783
Display apparatus, method of manufacturing the same, and electronic device Jan 20, 2022 Issued
Array ( [id] => 19470722 [patent_doc_number] => 20240324392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Display Device And Method For Manufacturing Display Device [patent_app_type] => utility [patent_app_number] => 18/273860 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18273860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/273860
Display Device And Method For Manufacturing Display Device Jan 17, 2022 Pending
Array ( [id] => 19470722 [patent_doc_number] => 20240324392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Display Device And Method For Manufacturing Display Device [patent_app_type] => utility [patent_app_number] => 18/273860 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18273860 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/273860
Display Device And Method For Manufacturing Display Device Jan 17, 2022 Pending
Array ( [id] => 20443088 [patent_doc_number] => 12513934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/576840 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3150 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 481 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576840 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/576840
Semiconductor device Jan 13, 2022 Issued
Array ( [id] => 20443088 [patent_doc_number] => 12513934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/576840 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3150 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 481 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576840 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/576840
Semiconductor device Jan 13, 2022 Issued
Array ( [id] => 17833827 [patent_doc_number] => 20220271131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/568963 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568963
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME Jan 4, 2022 Abandoned
Array ( [id] => 18456527 [patent_doc_number] => 20230197809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SEMICONDUCTOR STRUCTURE HAVING A FIN STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/554813 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/554813
SEMICONDUCTOR STRUCTURE HAVING A FIN STRUCTURE Dec 16, 2021 Abandoned
Array ( [id] => 18456489 [patent_doc_number] => 20230197771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => MEMORY DEVICE HAVING WORD LINES WITH REDUCED LEAKAGE [patent_app_type] => utility [patent_app_number] => 17/552882 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552882
MEMORY DEVICE HAVING WORD LINES WITH REDUCED LEAKAGE Dec 15, 2021 Abandoned
Array ( [id] => 17509343 [patent_doc_number] => 20220102446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/547185 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547185
DISPLAY DEVICE Dec 8, 2021 Pending
Array ( [id] => 18424150 [patent_doc_number] => 20230178614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/544410 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544410 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544410
Semiconductor device and method for manufacturing the same Dec 6, 2021 Issued
Array ( [id] => 17840785 [patent_doc_number] => 20220278091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => CIRCUITS DESIGNED AND MANUFACTURED WITH FIRST AND SECOND FIN BOUNDARIES [patent_app_type] => utility [patent_app_number] => 17/543255 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543255 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543255
Circuits designed and manufactured with first and second fin boundaries Dec 5, 2021 Issued
Array ( [id] => 17840785 [patent_doc_number] => 20220278091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => CIRCUITS DESIGNED AND MANUFACTURED WITH FIRST AND SECOND FIN BOUNDARIES [patent_app_type] => utility [patent_app_number] => 17/543255 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543255 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543255
Circuits designed and manufactured with first and second fin boundaries Dec 5, 2021 Issued
Array ( [id] => 17644354 [patent_doc_number] => 20220172093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => METHOD OF MAKING A QUANTUM DEVICE [patent_app_type] => utility [patent_app_number] => 17/456388 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456388
Method of making a quantum device Nov 23, 2021 Issued
Array ( [id] => 20175014 [patent_doc_number] => 12393762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Method for generating a layout diagram of a semiconductor device including power-grid- adapted route-spacing [patent_app_type] => utility [patent_app_number] => 17/525375 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525375 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525375
Method for generating a layout diagram of a semiconductor device including power-grid- adapted route-spacing Nov 11, 2021 Issued
Array ( [id] => 18347211 [patent_doc_number] => 20230135321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => INTEGRATED SHORT CHANNEL OMEGA GATE FINFET AND LONG CHANNEL FINFET [patent_app_type] => utility [patent_app_number] => 17/517924 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517924
Integrated short channel omega gate FinFET and long channel FinFET Nov 2, 2021 Issued
Array ( [id] => 19945386 [patent_doc_number] => 12317536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Semiconductor device and power switching system including the same [patent_app_type] => utility [patent_app_number] => 17/517987 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9750 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517987 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517987
Semiconductor device and power switching system including the same Nov 2, 2021 Issued
Array ( [id] => 18849102 [patent_doc_number] => 20230411506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => NITRIDE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/247705 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18247705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/247705
NITRIDE SEMICONDUCTOR DEVICE Oct 6, 2021 Pending
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