Search

Valerie N. Newton

Examiner (ID: 2467, Phone: (571)270-5015 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2829, 2823, 4122
Total Applications
1018
Issued Applications
802
Pending Applications
97
Abandoned Applications
153

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9184284 [patent_doc_number] => 08624220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Nitride semiconductor' [patent_app_type] => utility [patent_app_number] => 13/112564 [patent_app_country] => US [patent_app_date] => 2011-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 43 [patent_no_of_words] => 50531 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13112564 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/112564
Nitride semiconductor May 19, 2011 Issued
Array ( [id] => 7577225 [patent_doc_number] => 20110291107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'SELF-ALIGNED SEMICONDUCTOR DEVICES WITH REDUCED GATE-SOURCE LEAKAGE UNDER REVERSE BIAS AND METHODS OF MAKING' [patent_app_type] => utility [patent_app_number] => 13/112075 [patent_app_country] => US [patent_app_date] => 2011-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3196 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291107.pdf [firstpage_image] =>[orig_patent_app_number] => 13112075 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/112075
Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making May 19, 2011 Issued
Array ( [id] => 5932571 [patent_doc_number] => 20110210445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING VIA CONNECTING BETWEEN INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 13/104484 [patent_app_country] => US [patent_app_date] => 2011-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 19610 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20110210445.pdf [firstpage_image] =>[orig_patent_app_number] => 13104484 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/104484
Semiconductor device having via connecting between interconnects May 9, 2011 Issued
Array ( [id] => 6169721 [patent_doc_number] => 20110175091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/075436 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17365 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20110175091.pdf [firstpage_image] =>[orig_patent_app_number] => 13075436 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075436
Display device and manufacturing method thereof Mar 29, 2011 Issued
Array ( [id] => 9020350 [patent_doc_number] => 08530335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/071629 [patent_app_country] => US [patent_app_date] => 2011-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 84 [patent_no_of_words] => 25009 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13071629 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/071629
Method for manufacturing semiconductor device Mar 24, 2011 Issued
Array ( [id] => 8652930 [patent_doc_number] => 08372676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Integrated getter area for wafer level encapsulated microelectromechanical systems' [patent_app_type] => utility [patent_app_number] => 13/050099 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 7881 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13050099 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/050099
Integrated getter area for wafer level encapsulated microelectromechanical systems Mar 16, 2011 Issued
Array ( [id] => 8403102 [patent_doc_number] => 20120235167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'SOLID STATE OPTOELECTRONIC DEVICE WITH PREFORMED METAL SUPPORT SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/048656 [patent_app_country] => US [patent_app_date] => 2011-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3942 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13048656 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/048656
Solid state optoelectronic device with preformed metal support substrate Mar 14, 2011 Issued
Array ( [id] => 8185551 [patent_doc_number] => 20120115324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A REFRACTORY METAL CONTAINING FILM' [patent_app_type] => utility [patent_app_number] => 13/014282 [patent_app_country] => US [patent_app_date] => 2011-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9565 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20120115324.pdf [firstpage_image] =>[orig_patent_app_number] => 13014282 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/014282
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A REFRACTORY METAL CONTAINING FILM Jan 25, 2011 Abandoned
Array ( [id] => 8713123 [patent_doc_number] => 08399264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Alignment inspection' [patent_app_type] => utility [patent_app_number] => 12/957169 [patent_app_country] => US [patent_app_date] => 2010-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3259 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12957169 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/957169
Alignment inspection Nov 29, 2010 Issued
Array ( [id] => 6185488 [patent_doc_number] => 20110124205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'TUNING OF PHOTO-ABSORPTION MATERIALS THROUGH USE OF MAGNETIC FIELDS' [patent_app_type] => utility [patent_app_number] => 12/950816 [patent_app_country] => US [patent_app_date] => 2010-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20110124205.pdf [firstpage_image] =>[orig_patent_app_number] => 12950816 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/950816
Tuning of photo-absorption materials through use of magnetic fields Nov 18, 2010 Issued
Array ( [id] => 6185487 [patent_doc_number] => 20110124204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, AND SUBSTRATE PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/950340 [patent_app_country] => US [patent_app_date] => 2010-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 21738 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20110124204.pdf [firstpage_image] =>[orig_patent_app_number] => 12950340 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/950340
Method of manufacturing semiconductor device, method of processing substrate, and substrate processing apparatus Nov 18, 2010 Issued
Array ( [id] => 8469740 [patent_doc_number] => 08298918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Method for forming semiconductor layer and method for manufacturing light emitting device' [patent_app_type] => utility [patent_app_number] => 12/948085 [patent_app_country] => US [patent_app_date] => 2010-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3593 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12948085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/948085
Method for forming semiconductor layer and method for manufacturing light emitting device Nov 16, 2010 Issued
Array ( [id] => 11564729 [patent_doc_number] => 09627324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Apparatus and method for processing a substrate' [patent_app_type] => utility [patent_app_number] => 12/947912 [patent_app_country] => US [patent_app_date] => 2010-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 34 [patent_no_of_words] => 11060 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12947912 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/947912
Apparatus and method for processing a substrate Nov 16, 2010 Issued
Array ( [id] => 8005821 [patent_doc_number] => 08084311 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-27 [patent_title] => 'Method of forming replacement metal gate with borderless contact and structure thereof' [patent_app_type] => utility [patent_app_number] => 12/948246 [patent_app_country] => US [patent_app_date] => 2010-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4626 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/084/08084311.pdf [firstpage_image] =>[orig_patent_app_number] => 12948246 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/948246
Method of forming replacement metal gate with borderless contact and structure thereof Nov 16, 2010 Issued
Array ( [id] => 6185425 [patent_doc_number] => 20110124186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'APPARATUS AND METHOD FOR CONTROLLABLY IMPLANTING WORKPIECES' [patent_app_type] => utility [patent_app_number] => 12/947078 [patent_app_country] => US [patent_app_date] => 2010-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7341 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20110124186.pdf [firstpage_image] =>[orig_patent_app_number] => 12947078 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/947078
Apparatus and method for controllably implanting workpieces Nov 15, 2010 Issued
Array ( [id] => 6199710 [patent_doc_number] => 20110062496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'Methods and Compositions for Preparing Ge/Si Semiconductor Substrates' [patent_app_type] => utility [patent_app_number] => 12/946485 [patent_app_country] => US [patent_app_date] => 2010-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13981 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20110062496.pdf [firstpage_image] =>[orig_patent_app_number] => 12946485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/946485
Methods and Compositions for Preparing Ge/Si Semiconductor Substrates Nov 14, 2010 Abandoned
Array ( [id] => 7729402 [patent_doc_number] => 08101480 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-24 [patent_title] => 'Methods of forming transistors and CMOS semiconductor devices using an SMT technique' [patent_app_type] => utility [patent_app_number] => 12/944774 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 39 [patent_no_of_words] => 12008 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/101/08101480.pdf [firstpage_image] =>[orig_patent_app_number] => 12944774 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/944774
Methods of forming transistors and CMOS semiconductor devices using an SMT technique Nov 11, 2010 Issued
Array ( [id] => 8664337 [patent_doc_number] => 08377798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Method and structure for wafer to wafer bonding in semiconductor packaging' [patent_app_type] => utility [patent_app_number] => 12/943281 [patent_app_country] => US [patent_app_date] => 2010-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 4531 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12943281 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/943281
Method and structure for wafer to wafer bonding in semiconductor packaging Nov 9, 2010 Issued
Array ( [id] => 8185536 [patent_doc_number] => 20120115319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'CONTACT PAD' [patent_app_type] => utility [patent_app_number] => 12/943517 [patent_app_country] => US [patent_app_date] => 2010-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5178 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20120115319.pdf [firstpage_image] =>[orig_patent_app_number] => 12943517 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/943517
Contact pad Nov 9, 2010 Issued
Array ( [id] => 8185451 [patent_doc_number] => 20120115284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/943015 [patent_app_country] => US [patent_app_date] => 2010-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5382 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20120115284.pdf [firstpage_image] =>[orig_patent_app_number] => 12943015 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/943015
Method for manufacturing multi-gate transistor device Nov 9, 2010 Issued
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