
Valerie N. Newton
Examiner (ID: 2467, Phone: (571)270-5015 , Office: P/2897 )
| Most Active Art Unit | 2897 |
| Art Unit(s) | 2897, 2829, 2823, 4122 |
| Total Applications | 1018 |
| Issued Applications | 802 |
| Pending Applications | 97 |
| Abandoned Applications | 153 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5364876
[patent_doc_number] => 20090302435
[patent_country] => US
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[patent_issue_date] => 2009-12-10
[patent_title] => 'Semiconductor Device and Method of Shielding Semiconductor Die from Inter-Device Interference'
[patent_app_type] => utility
[patent_app_number] => 12/133216
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/133216 | Semiconductor device and method of shielding semiconductor die from inter-device interference | Jun 3, 2008 | Issued |
Array
(
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[patent_doc_number] => 20090209101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-20
[patent_title] => 'RUTHENIUM ALLOY FILM FOR COPPER INTERCONNECTS'
[patent_app_type] => utility
[patent_app_number] => 12/129345
[patent_app_country] => US
[patent_app_date] => 2008-05-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/129345 | Ruthenium alloy film for copper interconnects | May 28, 2008 | Issued |
Array
(
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[patent_issue_date] => 2011-10-25
[patent_title] => 'Method of forming aluminum oxide layer and method of manufacturing charge trap memory device using the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/153655 | Method of forming aluminum oxide layer and method of manufacturing charge trap memory device using the same | May 21, 2008 | Issued |
Array
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[patent_issue_date] => 2009-11-26
[patent_title] => 'CMOS Process with Optimized PMOS and NMOS Transistor Devices'
[patent_app_type] => utility
[patent_app_number] => 12/125855
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[patent_app_date] => 2008-05-22
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Array
(
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[patent_title] => 'Isolation structure for semiconductor integrated circuit substrate'
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Array
(
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[patent_title] => 'Method of forming isolation structure for semiconductor integrated circuit substrate'
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Array
(
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[patent_issue_date] => 2009-07-30
[patent_title] => 'Pixel structure and method for manufacturing the same'
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[patent_app_country] => US
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[patent_drawing_sheets_cnt] => 49
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/081515 | Pixel structure and method for manufacturing the same | Apr 16, 2008 | Abandoned |
Array
(
[id] => 4515183
[patent_doc_number] => 07932186
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-26
[patent_title] => 'Methods for fabricating an electronic device'
[patent_app_type] => utility
[patent_app_number] => 12/061866
[patent_app_country] => US
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[pdf_file] => patents/07/932/07932186.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/061866 | Methods for fabricating an electronic device | Apr 2, 2008 | Issued |
Array
(
[id] => 5473786
[patent_doc_number] => 20090246952
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[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'METHOD OF FORMING A COBALT METAL NITRIDE BARRIER FILM'
[patent_app_type] => utility
[patent_app_number] => 12/058595
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/058595 | METHOD OF FORMING A COBALT METAL NITRIDE BARRIER FILM | Mar 27, 2008 | Abandoned |
Array
(
[id] => 5473808
[patent_doc_number] => 20090246974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'METHOD OF FORMING A STRESSED PASSIVATION FILM USING A MICROWAVE-ASSISTED OXIDATION PROCESS'
[patent_app_type] => utility
[patent_app_number] => 12/058585
[patent_app_country] => US
[patent_app_date] => 2008-03-28
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 12058585
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/058585 | Method of forming a stressed passivation film using a microwave-assisted oxidation process | Mar 27, 2008 | Issued |
Array
(
[id] => 5508648
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[patent_country] => US
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[patent_title] => 'FABRICATION METHOD OF POLYSILICON LAYER'
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Array
(
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[patent_title] => 'PIEZOELECTRIC SUBSTRATE, FABRICATION AND RELATED METHODS'
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Array
(
[id] => 6070811
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/524151 | Low-temperature formation of layers of polycrystalline semiconductor material | Feb 18, 2008 | Issued |
Array
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[patent_title] => 'Plasma immersion ion implantation using an electrode with edge-effect suppression by a downwardly curving edge'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/022735 | Methods of Manufacturing Non-Volatile Memory Devices Including Charge-Trapping Layers | Jan 29, 2008 | Abandoned |
Array
(
[id] => 5340616
[patent_doc_number] => 20090179266
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[patent_kind] => A1
[patent_issue_date] => 2009-07-16
[patent_title] => 'DEVICE STRUCTURES FOR A METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND METHODS OF FABRICATING SUCH DEVICE STRUCTURES'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/972941 | Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures | Jan 10, 2008 | Issued |
Array
(
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[patent_issue_date] => 2011-09-20
[patent_title] => 'Semiconductor device and method for fabricating the same'
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Array
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[patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE INTEGRATION'
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Array
(
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[patent_country] => US
[patent_kind] => A1
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[patent_title] => 'METHOD AND APPARATUS FOR SINGULATING INTEGRATED CIRCUIT CHIPS'
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[patent_app_number] => 11/955495
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/955495 | METHOD AND APPARATUS FOR SINGULATING INTEGRATED CIRCUIT CHIPS | Dec 12, 2007 | Abandoned |
Array
(
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