Search

Valerie N. Newton

Examiner (ID: 2467, Phone: (571)270-5015 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2829, 2823, 4122
Total Applications
1018
Issued Applications
802
Pending Applications
97
Abandoned Applications
153

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5088933 [patent_doc_number] => 20070228572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Formation of an integrated circuit structure with reduced dishing in metallization levels' [patent_app_type] => utility [patent_app_number] => 11/649015 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1985 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20070228572.pdf [firstpage_image] =>[orig_patent_app_number] => 11649015 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/649015
Formation of an integrated circuit structure with reduced dishing in metallization levels Jan 2, 2007 Issued
Array ( [id] => 5028524 [patent_doc_number] => 20070269971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/618612 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1636 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20070269971.pdf [firstpage_image] =>[orig_patent_app_number] => 11618612 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618612
Method for manufacturing semiconductor device Dec 28, 2006 Issued
Array ( [id] => 4932998 [patent_doc_number] => 20080003773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Method for forming isolation structure of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/647635 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2777 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003773.pdf [firstpage_image] =>[orig_patent_app_number] => 11647635 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647635
Method for forming isolation structure of semiconductor device Dec 27, 2006 Abandoned
Array ( [id] => 5022979 [patent_doc_number] => 20070148945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'METHOD FOR FORMING A FINE PATTERN OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/616812 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1513 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148945.pdf [firstpage_image] =>[orig_patent_app_number] => 11616812 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616812
METHOD FOR FORMING A FINE PATTERN OF A SEMICONDUCTOR DEVICE Dec 26, 2006 Abandoned
Array ( [id] => 52862 [patent_doc_number] => 07772030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Multipurpose decapsulation holder and method for a ball grid array package' [patent_app_type] => utility [patent_app_number] => 11/615971 [patent_app_country] => US [patent_app_date] => 2006-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4951 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/772/07772030.pdf [firstpage_image] =>[orig_patent_app_number] => 11615971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615971
Multipurpose decapsulation holder and method for a ball grid array package Dec 22, 2006 Issued
Array ( [id] => 4977451 [patent_doc_number] => 20070218684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Method for fabricating storage node contact plug of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/643915 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2371 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20070218684.pdf [firstpage_image] =>[orig_patent_app_number] => 11643915 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643915
Method for fabricating storage node contact plug of semiconductor device Dec 21, 2006 Abandoned
Array ( [id] => 83394 [patent_doc_number] => 07741147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Method of field-controlled diffusion and devices formed thereby' [patent_app_type] => utility [patent_app_number] => 11/615331 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5858 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/741/07741147.pdf [firstpage_image] =>[orig_patent_app_number] => 11615331 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615331
Method of field-controlled diffusion and devices formed thereby Dec 21, 2006 Issued
Array ( [id] => 81627 [patent_doc_number] => 07745335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Semiconductor device manufactured by reducing hillock formation in metal interconnects' [patent_app_type] => utility [patent_app_number] => 11/614511 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4255 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/745/07745335.pdf [firstpage_image] =>[orig_patent_app_number] => 11614511 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/614511
Semiconductor device manufactured by reducing hillock formation in metal interconnects Dec 20, 2006 Issued
Array ( [id] => 5022946 [patent_doc_number] => 20070148912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Method for Manufacturing Direct Bonded SOI Wafer and Direct Bonded SOI Wafer Manufactured by the Method' [patent_app_type] => utility [patent_app_number] => 11/614681 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6664 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148912.pdf [firstpage_image] =>[orig_patent_app_number] => 11614681 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/614681
Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method Dec 20, 2006 Issued
Array ( [id] => 5019632 [patent_doc_number] => 20070145598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'METHOD OF FORMING A METAL INTERCONNECTION IN A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/613751 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145598.pdf [firstpage_image] =>[orig_patent_app_number] => 11613751 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/613751
METHOD OF FORMING A METAL INTERCONNECTION IN A SEMICONDUCTOR DEVICE Dec 19, 2006 Abandoned
Array ( [id] => 83510 [patent_doc_number] => 07741197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-22 [patent_title] => 'Systems and methods for harvesting and reducing contamination in nanowires' [patent_app_type] => utility [patent_app_number] => 11/643025 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 36 [patent_no_of_words] => 23351 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/741/07741197.pdf [firstpage_image] =>[orig_patent_app_number] => 11643025 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643025
Systems and methods for harvesting and reducing contamination in nanowires Dec 19, 2006 Issued
Array ( [id] => 74147 [patent_doc_number] => 07749893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Methods and systems for low interfacial oxide contact between barrier and copper metallization' [patent_app_type] => utility [patent_app_number] => 11/641361 [patent_app_country] => US [patent_app_date] => 2006-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8100 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/749/07749893.pdf [firstpage_image] =>[orig_patent_app_number] => 11641361 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/641361
Methods and systems for low interfacial oxide contact between barrier and copper metallization Dec 17, 2006 Issued
Array ( [id] => 800352 [patent_doc_number] => 07425495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'Method of manufacturing semiconductor substrate and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/639015 [patent_app_country] => US [patent_app_date] => 2006-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 26 [patent_no_of_words] => 4642 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 432 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/425/07425495.pdf [firstpage_image] =>[orig_patent_app_number] => 11639015 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/639015
Method of manufacturing semiconductor substrate and semiconductor device Dec 13, 2006 Issued
Array ( [id] => 5217386 [patent_doc_number] => 20070158697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'PHASE CHANGE MEMORY DEVICE USING CARBON NANOTUBE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/610341 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6276 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20070158697.pdf [firstpage_image] =>[orig_patent_app_number] => 11610341 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/610341
Phase change memory device using carbon nanotube and method for fabricating the same Dec 12, 2006 Issued
Array ( [id] => 4785675 [patent_doc_number] => 20080139004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Light emission from silicon-based nanocrystals by sequential thermal annealing approaches' [patent_app_type] => utility [patent_app_number] => 11/637405 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2273 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20080139004.pdf [firstpage_image] =>[orig_patent_app_number] => 11637405 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/637405
Light emission from silicon-based nanocrystals by sequential thermal annealing approaches Dec 11, 2006 Abandoned
Array ( [id] => 4583141 [patent_doc_number] => 07851361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Laser ablation to selectively thin wafers/die to lower device RDSON' [patent_app_type] => utility [patent_app_number] => 11/636762 [patent_app_country] => US [patent_app_date] => 2006-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/851/07851361.pdf [firstpage_image] =>[orig_patent_app_number] => 11636762 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/636762
Laser ablation to selectively thin wafers/die to lower device RDSON Dec 10, 2006 Issued
Array ( [id] => 4944128 [patent_doc_number] => 20080081453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Method of forming metal wire of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/603752 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2391 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20080081453.pdf [firstpage_image] =>[orig_patent_app_number] => 11603752 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/603752
Method of forming metal wire of semiconductor device Nov 21, 2006 Abandoned
Array ( [id] => 73947 [patent_doc_number] => 07749799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Back-illuminated imager and method for making electrical and optical connections to same' [patent_app_type] => utility [patent_app_number] => 11/600583 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 39 [patent_no_of_words] => 8340 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/749/07749799.pdf [firstpage_image] =>[orig_patent_app_number] => 11600583 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/600583
Back-illuminated imager and method for making electrical and optical connections to same Nov 14, 2006 Issued
Array ( [id] => 5113106 [patent_doc_number] => 20070197021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Semiconductor device including spacer with nitride/nitride/oxide structure and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/595308 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4336 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20070197021.pdf [firstpage_image] =>[orig_patent_app_number] => 11595308 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/595308
Semiconductor device including spacer with nitride/nitride/oxide structure and method for fabricating the same Nov 8, 2006 Abandoned
Array ( [id] => 5215787 [patent_doc_number] => 20070104868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Method and apparatus for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/593689 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2939 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20070104868.pdf [firstpage_image] =>[orig_patent_app_number] => 11593689 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/593689
Method and apparatus for manufacturing semiconductor device Nov 5, 2006 Abandoned
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