Search

Valerie N. Newton

Examiner (ID: 2467, Phone: (571)270-5015 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2829, 2823, 4122
Total Applications
1018
Issued Applications
802
Pending Applications
97
Abandoned Applications
153

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4692803 [patent_doc_number] => 20080085574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'ANTIFUSE ONE TIME PROGRAMMABLE MEMORY ARRAY AND METHOD OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 11/538862 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20080085574.pdf [firstpage_image] =>[orig_patent_app_number] => 11538862 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538862
Antifuse one time programmable memory array and method of manufacture Oct 4, 2006 Issued
Array ( [id] => 4582445 [patent_doc_number] => 07851257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Integrated circuit stacking system with integrated passive components' [patent_app_type] => utility [patent_app_number] => 11/538806 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/851/07851257.pdf [firstpage_image] =>[orig_patent_app_number] => 11538806 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538806
Integrated circuit stacking system with integrated passive components Oct 3, 2006 Issued
Array ( [id] => 4944162 [patent_doc_number] => 20080081487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Method for fabricating semiconductor element' [patent_app_type] => utility [patent_app_number] => 11/529289 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2356 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20080081487.pdf [firstpage_image] =>[orig_patent_app_number] => 11529289 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/529289
Method for fabricating semiconductor element Sep 28, 2006 Abandoned
Array ( [id] => 252610 [patent_doc_number] => 07579243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Split gate memory cell method' [patent_app_type] => utility [patent_app_number] => 11/535345 [patent_app_country] => US [patent_app_date] => 2006-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 5669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/579/07579243.pdf [firstpage_image] =>[orig_patent_app_number] => 11535345 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/535345
Split gate memory cell method Sep 25, 2006 Issued
Array ( [id] => 5056990 [patent_doc_number] => 20070059912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Method of forming metal silicide layer and related method of fabricating semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/519845 [patent_app_country] => US [patent_app_date] => 2006-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20070059912.pdf [firstpage_image] =>[orig_patent_app_number] => 11519845 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/519845
Method of forming metal silicide layer and related method of fabricating semiconductor devices Sep 12, 2006 Abandoned
Array ( [id] => 4772043 [patent_doc_number] => 20080057701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'METHOD FOR PREVENTION OF RESIST POISONING IN INTEGRATED CIRCUIT FABRICATION' [patent_app_type] => utility [patent_app_number] => 11/469598 [patent_app_country] => US [patent_app_date] => 2006-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20080057701.pdf [firstpage_image] =>[orig_patent_app_number] => 11469598 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/469598
METHOD FOR PREVENTION OF RESIST POISONING IN INTEGRATED CIRCUIT FABRICATION Aug 31, 2006 Abandoned
Array ( [id] => 4604641 [patent_doc_number] => 07985621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Method and apparatus for making semiconductor packages' [patent_app_type] => utility [patent_app_number] => 11/469256 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7891 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/985/07985621.pdf [firstpage_image] =>[orig_patent_app_number] => 11469256 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/469256
Method and apparatus for making semiconductor packages Aug 30, 2006 Issued
Array ( [id] => 217073 [patent_doc_number] => 07611983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Semiconductor device and a manufacturing method of the same' [patent_app_type] => utility [patent_app_number] => 11/513029 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 2888 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/611/07611983.pdf [firstpage_image] =>[orig_patent_app_number] => 11513029 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/513029
Semiconductor device and a manufacturing method of the same Aug 30, 2006 Issued
Array ( [id] => 4768757 [patent_doc_number] => 20080054413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'SELF-ALIGNED DUAL SEGMENT LINER AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/468536 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054413.pdf [firstpage_image] =>[orig_patent_app_number] => 11468536 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/468536
Self-aligned dual segment liner and method of manufacturing the same Aug 29, 2006 Issued
Array ( [id] => 5688446 [patent_doc_number] => 20060286761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Wet electrolytic capacitors' [patent_app_type] => utility [patent_app_number] => 11/510966 [patent_app_country] => US [patent_app_date] => 2006-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12489 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20060286761.pdf [firstpage_image] =>[orig_patent_app_number] => 11510966 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510966
Wet electrolytic capacitors Aug 27, 2006 Issued
Array ( [id] => 5217541 [patent_doc_number] => 20070158852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Circuit Board with Conductive Structure and Method for Fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/467296 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20070158852.pdf [firstpage_image] =>[orig_patent_app_number] => 11467296 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/467296
Circuit Board with Conductive Structure and Method for Fabricating the same Aug 24, 2006 Abandoned
Array ( [id] => 4669926 [patent_doc_number] => 20080044986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'METHOD FOR IMPROVED DIELECTRIC PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 11/465575 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7276 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20080044986.pdf [firstpage_image] =>[orig_patent_app_number] => 11465575 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465575
METHOD FOR IMPROVED DIELECTRIC PERFORMANCE Aug 17, 2006 Abandoned
Array ( [id] => 4999900 [patent_doc_number] => 20070042534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Chip Package and Package Process Thereof' [patent_app_type] => utility [patent_app_number] => 11/464296 [patent_app_country] => US [patent_app_date] => 2006-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3304 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20070042534.pdf [firstpage_image] =>[orig_patent_app_number] => 11464296 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464296
Chip package and package process thereof Aug 13, 2006 Issued
Array ( [id] => 5051437 [patent_doc_number] => 20070031982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Method of classifying defects and apparatus for performing the method' [patent_app_type] => utility [patent_app_number] => 11/462305 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4383 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20070031982.pdf [firstpage_image] =>[orig_patent_app_number] => 11462305 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/462305
Method of classifying defects and apparatus for performing the method Aug 2, 2006 Abandoned
Array ( [id] => 5154517 [patent_doc_number] => 20070037400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Composition and methods removing polysilicon' [patent_app_type] => utility [patent_app_number] => 11/495706 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20070037400.pdf [firstpage_image] =>[orig_patent_app_number] => 11495706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495706
Composition and methods removing polysilicon Jul 30, 2006 Abandoned
Array ( [id] => 5202312 [patent_doc_number] => 20070023791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'METHOD OF FABRICATING GATE OF FIN TYPE TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/460905 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4347 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20070023791.pdf [firstpage_image] =>[orig_patent_app_number] => 11460905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460905
Method of fabricating gate of fin type transistor Jul 27, 2006 Issued
Array ( [id] => 4564862 [patent_doc_number] => 07846838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Method for producing an electronic component' [patent_app_type] => utility [patent_app_number] => 11/997235 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5148 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/846/07846838.pdf [firstpage_image] =>[orig_patent_app_number] => 11997235 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/997235
Method for producing an electronic component Jul 26, 2006 Issued
Array ( [id] => 5205173 [patent_doc_number] => 20070026655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/489985 [patent_app_country] => US [patent_app_date] => 2006-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5815 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20070026655.pdf [firstpage_image] =>[orig_patent_app_number] => 11489985 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/489985
Method of manufacturing a semiconductor device Jul 19, 2006 Abandoned
Array ( [id] => 5730202 [patent_doc_number] => 20060255316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Etch solution for selectively removing silicon' [patent_app_type] => utility [patent_app_number] => 11/489694 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5730 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20060255316.pdf [firstpage_image] =>[orig_patent_app_number] => 11489694 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/489694
Etch solution for selectively removing silicon Jul 18, 2006 Abandoned
Array ( [id] => 5242349 [patent_doc_number] => 20070020844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Method for fabricating bit line of memory device' [patent_app_type] => utility [patent_app_number] => 11/490206 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1855 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020844.pdf [firstpage_image] =>[orig_patent_app_number] => 11490206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/490206
Method for fabricating bit line of memory device Jul 18, 2006 Abandoned
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