
Valerie N. Newton
Examiner (ID: 2467, Phone: (571)270-5015 , Office: P/2897 )
| Most Active Art Unit | 2897 |
| Art Unit(s) | 2897, 2829, 2823, 4122 |
| Total Applications | 1018 |
| Issued Applications | 802 |
| Pending Applications | 97 |
| Abandoned Applications | 153 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5016289
[patent_doc_number] => 20070259498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-08
[patent_title] => 'METHOD OF FABRICATING METAL-OXIDE-SEMICONDUCTOR TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 11/309205
[patent_app_country] => US
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0259/20070259498.pdf
[firstpage_image] =>[orig_patent_app_number] => 11309205
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/309205 | Method of fabricating metal-oxide-semiconductor transistor | Jul 12, 2006 | Issued |
Array
(
[id] => 5210537
[patent_doc_number] => 20070249121
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[patent_kind] => A1
[patent_issue_date] => 2007-10-25
[patent_title] => 'METHOD OF FABRICATING NON-VOLATILE MEMORY'
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[patent_app_number] => 11/309206
[patent_app_country] => US
[patent_app_date] => 2006-07-13
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Array
(
[id] => 4528380
[patent_doc_number] => 07923278
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-12
[patent_title] => 'Integrated getter area for wafer level encapsulated microelectromechanical systems'
[patent_app_type] => utility
[patent_app_number] => 11/484431
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[patent_app_date] => 2006-07-11
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[patent_drawing_sheets_cnt] => 31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/484431 | Integrated getter area for wafer level encapsulated microelectromechanical systems | Jul 10, 2006 | Issued |
Array
(
[id] => 263710
[patent_doc_number] => 07569474
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-04
[patent_title] => 'Method and apparatus for soldering modules to substrates'
[patent_app_type] => utility
[patent_app_number] => 11/483015
[patent_app_country] => US
[patent_app_date] => 2006-07-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/483015 | Method and apparatus for soldering modules to substrates | Jul 6, 2006 | Issued |
Array
(
[id] => 4825973
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[patent_issue_date] => 2008-05-29
[patent_title] => 'WAFER BONDING METHOD'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/309105 | WAFER BONDING METHOD | Jun 22, 2006 | Abandoned |
Array
(
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[patent_issue_date] => 2006-12-28
[patent_title] => 'Replacement gate field effect transistor with germanium or SiGe channel and manufacturing method for same using gas-cluster ion irradiation'
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[patent_app_number] => 11/472136
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Array
(
[id] => 578586
[patent_doc_number] => 07452733
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[patent_issue_date] => 2008-11-18
[patent_title] => 'Method of increasing reliability of packaged semiconductor integrated circuit dice'
[patent_app_type] => utility
[patent_app_number] => 11/451693
[patent_app_country] => US
[patent_app_date] => 2006-06-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/451693 | Method of increasing reliability of packaged semiconductor integrated circuit dice | Jun 12, 2006 | Issued |
Array
(
[id] => 5046113
[patent_doc_number] => 20070264786
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-15
[patent_title] => 'METHOD OF MANUFACTURING METAL OXIDE SEMICONDUCTOR TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 11/308825
[patent_app_country] => US
[patent_app_date] => 2006-05-11
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/308825 | METHOD OF MANUFACTURING METAL OXIDE SEMICONDUCTOR TRANSISTOR | May 10, 2006 | Abandoned |
Array
(
[id] => 195865
[patent_doc_number] => 07635643
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-22
[patent_title] => 'Method for forming C4 connections on integrated circuit chips and the resulting devices'
[patent_app_type] => utility
[patent_app_number] => 11/380215
[patent_app_country] => US
[patent_app_date] => 2006-04-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/380215 | Method for forming C4 connections on integrated circuit chips and the resulting devices | Apr 25, 2006 | Issued |
Array
(
[id] => 8642559
[patent_doc_number] => 08367543
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[patent_kind] => B2
[patent_issue_date] => 2013-02-05
[patent_title] => 'Structure and method to improve current-carrying capabilities of C4 joints'
[patent_app_type] => utility
[patent_app_number] => 11/308396
[patent_app_country] => US
[patent_app_date] => 2006-03-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/308396 | Structure and method to improve current-carrying capabilities of C4 joints | Mar 20, 2006 | Issued |
Array
(
[id] => 4986358
[patent_doc_number] => 20070152696
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[patent_issue_date] => 2007-07-05
[patent_title] => 'Water bond-out'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/385420 | Water bond-out | Mar 20, 2006 | Abandoned |
Array
(
[id] => 373345
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[patent_title] => 'Double exposure double resist layer process for forming gate patterns'
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Array
(
[id] => 8339072
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Array
(
[id] => 32580
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Array
(
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Array
(
[id] => 7492179
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Array
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Array
(
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