Search

Van Thu T. Nguyen

Examiner (ID: 947, Phone: (571)272-1881 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824, 2818
Total Applications
1819
Issued Applications
1543
Pending Applications
95
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18935211 [patent_doc_number] => 11887649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems [patent_app_type] => utility [patent_app_number] => 17/387428 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/387428
Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems Jul 27, 2021 Issued
Array ( [id] => 18494072 [patent_doc_number] => 11699493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Method and apparatus for performing a read of a flash memory using predicted retention-and-read-disturb-compensated threshold voltage shift offset values [patent_app_type] => utility [patent_app_number] => 17/385857 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7216 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17385857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/385857
Method and apparatus for performing a read of a flash memory using predicted retention-and-read-disturb-compensated threshold voltage shift offset values Jul 25, 2021 Issued
Array ( [id] => 17582619 [patent_doc_number] => 20220139474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => MEMORY CONTROLLER, MEMORY SYSTEM WITH IMPROVED THRESHOLD VOLTAGE DISTRIBUTION CHARACTERISTICS, AND OPERATION METHOD [patent_app_type] => utility [patent_app_number] => 17/384219 [patent_app_country] => US [patent_app_date] => 2021-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384219
Memory controller, memory system with improved threshold voltage distribution characteristics, and operation method Jul 22, 2021 Issued
Array ( [id] => 17416840 [patent_doc_number] => 20220051744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => MEMORY CONTROLLER WITH ADAPTIVE REFRESH RATE CONTROLLED BY ERROR BIT INFORMATION [patent_app_type] => utility [patent_app_number] => 17/377350 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377350
MEMORY CONTROLLER WITH ADAPTIVE REFRESH RATE CONTROLLED BY ERROR BIT INFORMATION Jul 14, 2021 Abandoned
Array ( [id] => 19356699 [patent_doc_number] => 12057154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Method for efficiently waking up ferroelectric memory [patent_app_type] => utility [patent_app_number] => 17/370144 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 38 [patent_no_of_words] => 11072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370144 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370144
Method for efficiently waking up ferroelectric memory Jul 7, 2021 Issued
Array ( [id] => 17188537 [patent_doc_number] => 20210335422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => METHOD OF OPERATING RESISTIVE MEMORY DEVICE TO INCREASE READ MARGIN [patent_app_type] => utility [patent_app_number] => 17/369211 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369211 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369211
Method of operating resistive memory device to increase read margin Jul 6, 2021 Issued
Array ( [id] => 17508827 [patent_doc_number] => 20220101930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/359688 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359688 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359688
Nonvolatile memory device and operation method of detecting defective memory cells Jun 27, 2021 Issued
Array ( [id] => 18528516 [patent_doc_number] => 11715514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Latch bit cells [patent_app_type] => utility [patent_app_number] => 17/359209 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 4512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359209
Latch bit cells Jun 24, 2021 Issued
Array ( [id] => 17173804 [patent_doc_number] => 20210327475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => Configuring a Host Interface of a Memory Device Based on Mode of Operation [patent_app_type] => utility [patent_app_number] => 17/356431 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356431
Configuring a host interface of a memory device based on mode of operation Jun 22, 2021 Issued
Array ( [id] => 17173805 [patent_doc_number] => 20210327476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND OPERATION METHOD OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/355765 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/355765
Memory device, memory system, and operation method of memory device Jun 22, 2021 Issued
Array ( [id] => 17708228 [patent_doc_number] => 20220208236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SEMICONDUCTOR DEVICE FOR SETTING OPTIONS OF I/O INTERFACE CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/346708 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346708 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346708
Semiconductor device for setting options of I/O interface circuits Jun 13, 2021 Issued
Array ( [id] => 17660488 [patent_doc_number] => 20220180953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/344264 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344264
STORAGE DEVICE AND OPERATING METHOD THEREOF Jun 9, 2021 Abandoned
Array ( [id] => 17115286 [patent_doc_number] => 20210295883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => MEMORY SYSTEM CAPABLE OF IMPROVING STABILITY OF A DATA READ OPERATION OF INTERFACE CIRCUIT, AND METHOD OF OPERATING THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/343046 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343046
Memory system capable of improving stability of a data read operation of interface circuit, and method of operating the memory system Jun 8, 2021 Issued
Array ( [id] => 17115285 [patent_doc_number] => 20210295882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => MEMORY SYSTEM CAPABLE OF IMPROVING STABILITY OF A DATA READ OPERATION OF INTERFACE CIRCUIT, AND METHOD OF OPERATING THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/343027 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343027 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343027
Memory system capable of improving stability of a data read operation of interface circuit, and method of operating the memory system Jun 8, 2021 Issued
Array ( [id] => 18061474 [patent_doc_number] => 20220392560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => ADJUSTABLE PROGRAMMING PULSES FOR A MULTI-LEVEL CELL [patent_app_type] => utility [patent_app_number] => 17/337195 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/337195
Adjustable programming pulses for a multi-level cell Jun 1, 2021 Issued
Array ( [id] => 17431430 [patent_doc_number] => 20220059139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHOD OF GENERATING A MULTI-LEVEL SIGNAL USING A SELECTIVE LEVEL CHANGE, A METHOD OF TRANSMITTING DATA USING THE SAME, AND A TRANSMITTER AND MEMORY SYSTEM PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/323009 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323009 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323009
Method of generating a multi-level signal using a selective level change, a method of transmitting data using the same, and a transmitter and memory system performing the same May 17, 2021 Issued
Array ( [id] => 18304262 [patent_doc_number] => 11626175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Memory system and operating method for determining target memory block for refreshing operation [patent_app_type] => utility [patent_app_number] => 17/321649 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11009 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/321649
Memory system and operating method for determining target memory block for refreshing operation May 16, 2021 Issued
Array ( [id] => 18008232 [patent_doc_number] => 20220366999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Adaptive Read Disturb Algorithm For Nand Storage Accounting For Layer-Based Effect [patent_app_type] => utility [patent_app_number] => 17/322543 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322543
Adaptive read disturb algorithm for NAND storage accounting for layer-based effect May 16, 2021 Issued
Array ( [id] => 18593137 [patent_doc_number] => 11742046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Semiconductor memory device and operation method of swizzling data [patent_app_type] => utility [patent_app_number] => 17/318234 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 13892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318234
Semiconductor memory device and operation method of swizzling data May 11, 2021 Issued
Array ( [id] => 17795335 [patent_doc_number] => 20220254427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => APPARATUS CONFIGURED TO PERFORM A TEST OPERATION [patent_app_type] => utility [patent_app_number] => 17/306603 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306603 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306603
Apparatus configured to perform a test operation May 2, 2021 Issued
Menu