Search

Van Thu T. Nguyen

Examiner (ID: 947, Phone: (571)272-1881 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824, 2818
Total Applications
1819
Issued Applications
1543
Pending Applications
95
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17956148 [patent_doc_number] => 11482261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Memory device and method of operating with different input/output modes [patent_app_type] => utility [patent_app_number] => 17/242988 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 16042 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242988 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242988
Memory device and method of operating with different input/output modes Apr 27, 2021 Issued
Array ( [id] => 18593099 [patent_doc_number] => 11742008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Memory device with a clocking mechanism [patent_app_type] => utility [patent_app_number] => 17/240921 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7017 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240921
Memory device with a clocking mechanism Apr 25, 2021 Issued
Array ( [id] => 18357671 [patent_doc_number] => 11646077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Memory sub-system grading and allocation [patent_app_type] => utility [patent_app_number] => 17/240014 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240014
Memory sub-system grading and allocation Apr 25, 2021 Issued
Array ( [id] => 17551345 [patent_doc_number] => 20220122687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/238957 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17238957 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/238957
Page buffer, memory device including the page buffer and operating method thereof Apr 22, 2021 Issued
Array ( [id] => 18031793 [patent_doc_number] => 11514988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Controller and method of operating under sudden power interruption [patent_app_type] => utility [patent_app_number] => 17/238784 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 14257 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17238784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/238784
Controller and method of operating under sudden power interruption Apr 22, 2021 Issued
Array ( [id] => 17010643 [patent_doc_number] => 20210241804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => APPARATUS AND METHOD FOR IMPROVING INPUT/OUTPUT THROUGHPUT OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/234624 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234624 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/234624
Apparatus and method for improving input/output throughput of memory system Apr 18, 2021 Issued
Array ( [id] => 18623585 [patent_doc_number] => 11756638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => End of life performance throttling to prevent data loss [patent_app_type] => utility [patent_app_number] => 17/232804 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232804 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232804
End of life performance throttling to prevent data loss Apr 15, 2021 Issued
Array ( [id] => 18304316 [patent_doc_number] => 11626229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Switching of perpendicularly magnetized nanomagnets with spin-orbit torques in the absence of external magnetic fields [patent_app_type] => utility [patent_app_number] => 17/231277 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2716 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/231277
Switching of perpendicularly magnetized nanomagnets with spin-orbit torques in the absence of external magnetic fields Apr 14, 2021 Issued
Array ( [id] => 19487099 [patent_doc_number] => 12106823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Semiconductor device using transistors having low off-state current [patent_app_type] => utility [patent_app_number] => 17/914845 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 60 [patent_no_of_words] => 33495 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17914845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/914845
Semiconductor device using transistors having low off-state current Apr 5, 2021 Issued
Array ( [id] => 17764532 [patent_doc_number] => 20220238145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => METHOD AND SYSTEM FOR ASYNCHRONOUS MULTI-PLANE INDEPENDENT (AMPI) MEMORY READ OPERATION [patent_app_type] => utility [patent_app_number] => 17/214150 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214150 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214150
Method and system for asynchronous multi-plane independent (AMPI) memory read operation Mar 25, 2021 Issued
Array ( [id] => 16951430 [patent_doc_number] => 20210210122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => CHARGE PUMP SUPPLY OPTIMIZATION AND NOISE REDUCTION METHOD FOR LOGIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/205705 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/205705
Charge pump supply optimization and noise reduction method for logic systems Mar 17, 2021 Issued
Array ( [id] => 16934576 [patent_doc_number] => 20210200465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => DIRECT DATA TRANSFER IN MEMORY AND BETWEEN DEVICES OF A MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 17/200299 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200299
DIRECT DATA TRANSFER IN MEMORY AND BETWEEN DEVICES OF A MEMORY MODULE Mar 11, 2021 Abandoned
Array ( [id] => 17431432 [patent_doc_number] => 20220059141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/184351 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13621 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184351 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184351
Memory device with temperature information controller and operating method of the memory device Feb 23, 2021 Issued
Array ( [id] => 17347869 [patent_doc_number] => 20220014200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => INTEGRATED CIRCUITS HAVING MEMORY WITH FLEXIBLE INPUT-OUTPUT CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/181973 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181973 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181973
Integrated circuits having memory with flexible input-output circuits Feb 21, 2021 Issued
Array ( [id] => 17668099 [patent_doc_number] => 11361802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Logic compatible embedded flash memory [patent_app_type] => utility [patent_app_number] => 17/173646 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 10454 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173646 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173646
Logic compatible embedded flash memory Feb 10, 2021 Issued
Array ( [id] => 17188513 [patent_doc_number] => 20210335398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/164273 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17164273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/164273
Semiconductor memory device having a first plane and a second plane including respective latch circuits, and first and second FIFO circuits for fetching read data from the latch circuits Jan 31, 2021 Issued
Array ( [id] => 17359651 [patent_doc_number] => 20220020447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => MEMORY SYSTEM, MEMORY CONTROLLER, AND METHOD FOR OPERATING MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/162544 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162544 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162544
Memory system, memory controller, and method for operating memory system performing integrity check operation on target code when voltage drop is detected Jan 28, 2021 Issued
Array ( [id] => 17971109 [patent_doc_number] => 11488656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Write techniques for a memory device with a charge transfer device [patent_app_type] => utility [patent_app_number] => 17/157820 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 25708 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157820
Write techniques for a memory device with a charge transfer device Jan 24, 2021 Issued
Array ( [id] => 16811781 [patent_doc_number] => 20210134336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => MEMORY DEVICE INCLUDING INTERFACE CIRCUIT AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/150307 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150307 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150307
Memory device including interface circuit and method of operating the same Jan 14, 2021 Issued
Array ( [id] => 17054249 [patent_doc_number] => 20210263683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => MANAGEMENT OF NON-VOLATILE MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 17/147203 [patent_app_country] => US [patent_app_date] => 2021-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147203 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147203
MANAGEMENT OF NON-VOLATILE MEMORY ARRAYS Jan 11, 2021 Pending
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