Search

Van Thu T. Nguyen

Examiner (ID: 16561, Phone: (571)272-1881 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2824
Total Applications
1823
Issued Applications
1543
Pending Applications
96
Abandoned Applications
211

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16803106 [patent_doc_number] => 10998057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Storage device and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/846985 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846985 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/846985
Storage device and method of operating the same Apr 12, 2020 Issued
Array ( [id] => 17757958 [patent_doc_number] => 11398256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Local bit lines and methods of selecting the same to access memory elements in cross-point arrays [patent_app_type] => utility [patent_app_number] => 16/844487 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 10334 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844487 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/844487
Local bit lines and methods of selecting the same to access memory elements in cross-point arrays Apr 8, 2020 Issued
Array ( [id] => 16180133 [patent_doc_number] => 20200227102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => WORD LINE DECODER MEMORY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/831592 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831592 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831592
Word line decoder memory architecture Mar 25, 2020 Issued
Array ( [id] => 16379102 [patent_doc_number] => 20200327945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => RANDOM BIT CELL USING P-TYPE TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/830296 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830296 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/830296
Random bit cell using P-type transistors Mar 25, 2020 Issued
Array ( [id] => 16715381 [patent_doc_number] => 20210082528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => MEMORY SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 16/817371 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16817371 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/817371
Memory system controlling a threshold voltage in a read operation and method Mar 11, 2020 Issued
Array ( [id] => 16471420 [patent_doc_number] => 20200372958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => SEMICONDUCTOR APPARATUS AND CONTINUOUS READOUT METHOD [patent_app_type] => utility [patent_app_number] => 16/813728 [patent_app_country] => US [patent_app_date] => 2020-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813728 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/813728
Semiconductor apparatus and continuous readout method Mar 8, 2020 Issued
Array ( [id] => 16096441 [patent_doc_number] => 20200202207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => NEURAL NETWORK COMPUTATION CIRCUIT INCLUDING NON-VOLATILE SEMICONDUCTOR MEMORY ELEMENT [patent_app_type] => utility [patent_app_number] => 16/809359 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809359 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/809359
Neural network computation circuit including non-volatile semiconductor memory element Mar 3, 2020 Issued
Array ( [id] => 16920139 [patent_doc_number] => 20210193231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => MANAGING READ VOLTAGE LEVEL OF DATA UNITS IN A MEMORY DEVICE USING PROGRAM-TIME PROXIMITY [patent_app_type] => utility [patent_app_number] => 16/807739 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/807739
MANAGING READ VOLTAGE LEVEL OF DATA UNITS IN A MEMORY DEVICE USING PROGRAM-TIME PROXIMITY Mar 2, 2020 Abandoned
Array ( [id] => 16715327 [patent_doc_number] => 20210082474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/806997 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/806997
Memory system having plural circuits separately disposed from memories Mar 1, 2020 Issued
Array ( [id] => 17070424 [patent_doc_number] => 20210272641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => READ THRESHOLD OPTIMIZATION SYSTEMS AND METHODS BY MULTI-DIMENSIONAL SEARCH [patent_app_type] => utility [patent_app_number] => 16/804211 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16804211 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/804211
Read threshold optimization systems and methods by multi-dimensional search Feb 27, 2020 Issued
Array ( [id] => 16272028 [patent_doc_number] => 20200273516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SENSING A MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/801676 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801676 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/801676
SENSING A MEMORY CELL Feb 25, 2020 Abandoned
Array ( [id] => 16119211 [patent_doc_number] => 20200211628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => STORAGE DEVICE, DRIVING METHOD THEREOF, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/796140 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796140 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796140
Storage device applying a cancel circuit Feb 19, 2020 Issued
Array ( [id] => 17210455 [patent_doc_number] => 11170830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Word line driver for low voltage operation [patent_app_type] => utility [patent_app_number] => 16/787415 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16787415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/787415
Word line driver for low voltage operation Feb 10, 2020 Issued
Array ( [id] => 16759572 [patent_doc_number] => 10978127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Ferroelectric random access memory sensing scheme [patent_app_type] => utility [patent_app_number] => 16/784712 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6254 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784712 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784712
Ferroelectric random access memory sensing scheme Feb 6, 2020 Issued
Array ( [id] => 17018156 [patent_doc_number] => 11087801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-10 [patent_title] => Configuring a host interface of a memory device based on mode of operation [patent_app_type] => utility [patent_app_number] => 16/783611 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7731 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16783611 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/783611
Configuring a host interface of a memory device based on mode of operation Feb 5, 2020 Issued
Array ( [id] => 16738719 [patent_doc_number] => 10964380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-30 [patent_title] => Integrated device comprising memory bitcells comprising shared preload line and shared activation line [patent_app_type] => utility [patent_app_number] => 16/784149 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 11344 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784149 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784149
Integrated device comprising memory bitcells comprising shared preload line and shared activation line Feb 5, 2020 Issued
Array ( [id] => 17326292 [patent_doc_number] => 11217317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Memory device capable of improving a threshold voltage distribution of memory cells and method of operating the memory device [patent_app_type] => utility [patent_app_number] => 16/784160 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9109 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784160
Memory device capable of improving a threshold voltage distribution of memory cells and method of operating the memory device Feb 5, 2020 Issued
Array ( [id] => 17137472 [patent_doc_number] => 11139037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Semiconductor memory device including a first memory cell and a second memory cell that share a well region [patent_app_type] => utility [patent_app_number] => 16/783782 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 19017 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16783782 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/783782
Semiconductor memory device including a first memory cell and a second memory cell that share a well region Feb 5, 2020 Issued
Array ( [id] => 16765291 [patent_doc_number] => 20210110873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => Four Gate, Split-Gate Flash Memory Array With Byte Erase Operation [patent_app_type] => utility [patent_app_number] => 16/784183 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784183 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784183
Four gate, split-gate flash memory array with byte erase operation Feb 5, 2020 Issued
Array ( [id] => 17010658 [patent_doc_number] => 20210241819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => Dual SLC/QLC Programming and Resource Releasing [patent_app_type] => utility [patent_app_number] => 16/781885 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16781885 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/781885
Dual SLC/QLC programming and resource releasing Feb 3, 2020 Issued
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