Search

Van Thu T. Nguyen

Examiner (ID: 16561, Phone: (571)272-1881 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2818, 2824
Total Applications
1823
Issued Applications
1543
Pending Applications
96
Abandoned Applications
211

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17227900 [patent_doc_number] => 20210354456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => COMMUNICATING PRINT COMPONENT [patent_app_type] => utility [patent_app_number] => 16/956703 [patent_app_country] => US [patent_app_date] => 2019-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16956703 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/956703
Communicating print component Feb 5, 2019 Issued
Array ( [id] => 15184343 [patent_doc_number] => 20190362763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND OPERATION METHOD OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/262250 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262250 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262250
Memory device performing ZQ calibration, memory system, and operation method of memory device Jan 29, 2019 Issued
Array ( [id] => 15597145 [patent_doc_number] => 20200075107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => NAND FLASH MEMORY CONTROLLER AND STORAGE APPARATUS APPLYING THE SAME [patent_app_type] => utility [patent_app_number] => 16/244321 [patent_app_country] => US [patent_app_date] => 2019-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16244321 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/244321
NAND flash memory controller and storage apparatus applying the same Jan 9, 2019 Issued
Array ( [id] => 15369263 [patent_doc_number] => 20200020396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => METHOD OF WRITING DATA IN NONVOLATILE MEMORY DEVICE, METHOD OF ERASING DATA IN NONVOLATILE MEMORY DEVICE, AND NONVOLATILE MEMORY DEVICE PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/243281 [patent_app_country] => US [patent_app_date] => 2019-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16243281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/243281
Method of writing data in nonvolatile memory device, with divided subpages or subblocks, and method of erasing data in nonvolatile memory device with divided subpages or subblocks Jan 8, 2019 Issued
Array ( [id] => 15624985 [patent_doc_number] => 20200082897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => COLUMN SKIP INCONSISTENCY CORRECTION [patent_app_type] => utility [patent_app_number] => 16/239517 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239517
Column skip inconsistency correction Jan 2, 2019 Issued
Array ( [id] => 16409790 [patent_doc_number] => 10818354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Semiconductor memory having volatile and multi-bit non-volatile functionality and method of operating [patent_app_type] => utility [patent_app_number] => 16/239456 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 9893 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239456 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239456
Semiconductor memory having volatile and multi-bit non-volatile functionality and method of operating Jan 2, 2019 Issued
Array ( [id] => 16186883 [patent_doc_number] => 10720219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Semiconductor memory device and memory system that performs a normal read operation or a special read operation including a tracking read followed by a shift read [patent_app_type] => utility [patent_app_number] => 16/238400 [patent_app_country] => US [patent_app_date] => 2019-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 11580 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16238400 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/238400
Semiconductor memory device and memory system that performs a normal read operation or a special read operation including a tracking read followed by a shift read Jan 1, 2019 Issued
Array ( [id] => 15745251 [patent_doc_number] => 20200111515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => HIGH-SPEED DATA READOUT APPARATUS AND CMOS IMAGE SENSOR USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/237257 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237257
High-speed data readout apparatus and CMOS image sensor using the same Dec 30, 2018 Issued
Array ( [id] => 16080169 [patent_doc_number] => 20200194071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => NONVOLATILE MEMORY WITH A TEMPERATURE RECORDING FUNCTION AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/236609 [patent_app_country] => US [patent_app_date] => 2018-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236609 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236609
NONVOLATILE MEMORY WITH A TEMPERATURE RECORDING FUNCTION AND OPERATION METHOD THEREOF Dec 29, 2018 Abandoned
Array ( [id] => 16653146 [patent_doc_number] => 10930337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Write techniques for a memory device with a charge transfer device [patent_app_type] => utility [patent_app_number] => 16/232293 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 25658 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16232293 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/232293
Write techniques for a memory device with a charge transfer device Dec 25, 2018 Issued
Array ( [id] => 16233702 [patent_doc_number] => 10741262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => NAND flash operating techniques mitigating program disturbance [patent_app_type] => utility [patent_app_number] => 16/212551 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 7031 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16212551 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/212551
NAND flash operating techniques mitigating program disturbance Dec 5, 2018 Issued
Array ( [id] => 14413365 [patent_doc_number] => 20190172526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => SRAM MEMORY HAVING A FAST CLEAR [patent_app_type] => utility [patent_app_number] => 16/210663 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16210663 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/210663
SRAM MEMORY HAVING A FAST CLEAR Dec 4, 2018 Abandoned
Array ( [id] => 13998475 [patent_doc_number] => 20190068395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => INFORMATION PROVISION APPARATUS, SERVER APPARATUS, INFORMATION PROVISION METHOD, AND INFORMATION PROVISION PROGRAM [patent_app_type] => utility [patent_app_number] => 16/176107 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7926 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176107 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176107
Information provision apparatus, server apparatus, information provision method, and information provision program Oct 30, 2018 Issued
Array ( [id] => 13933621 [patent_doc_number] => 20190050326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => METHOD, FLASH MEMORY CONTROLLER, MEMORY DEVICE FOR ACCESSING 3D FLASH MEMORY HAVING MULTIPLE MEMORY CHIPS [patent_app_type] => utility [patent_app_number] => 16/159723 [patent_app_country] => US [patent_app_date] => 2018-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16159723 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/159723
Method, flashing memory controller, memory device for accessing 3D flash memory having multiple memory chips Oct 14, 2018 Issued
Array ( [id] => 16698520 [patent_doc_number] => 10949117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Direct data transfer in memory and between devices of a memory module [patent_app_type] => utility [patent_app_number] => 16/139935 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7399 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139935 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139935
Direct data transfer in memory and between devices of a memory module Sep 23, 2018 Issued
Array ( [id] => 14676061 [patent_doc_number] => 20190237145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/139627 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139627 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139627
Memory device detecting multiple program states and operating method thereof Sep 23, 2018 Issued
Array ( [id] => 16609042 [patent_doc_number] => 10910055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => System and method for reducing power consumption of memory device [patent_app_type] => utility [patent_app_number] => 16/137305 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 9309 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137305
System and method for reducing power consumption of memory device Sep 19, 2018 Issued
Array ( [id] => 15656381 [patent_doc_number] => 20200090721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => WORD LINE DECODER MEMORY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/134869 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16134869 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/134869
Word line decoder memory architecture Sep 17, 2018 Issued
Array ( [id] => 14842603 [patent_doc_number] => 20190279702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => FERROELECTRIC RANDOM ACCESS MEMORY SENSING SCHEME [patent_app_type] => utility [patent_app_number] => 16/111521 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111521 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/111521
Ferroelectric random access memory sensing scheme Aug 23, 2018 Issued
Array ( [id] => 15563887 [patent_doc_number] => 20200066355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => SELECTIVE PAGE CALIBRATION BASED ON HIERARCHICAL PAGE MAPPING [patent_app_type] => utility [patent_app_number] => 16/112392 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112392 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/112392
Selective page calibration based on hierarchical page mapping Aug 23, 2018 Issued
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