Search

Van Thu T. Nguyen

Examiner (ID: 947, Phone: (571)272-1881 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824, 2818
Total Applications
1819
Issued Applications
1543
Pending Applications
95
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20332586 [patent_doc_number] => 12462870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Reading a multi-level memory cell [patent_app_type] => utility [patent_app_number] => 18/643126 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 13493 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643126 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643126
Reading a multi-level memory cell Apr 22, 2024 Issued
Array ( [id] => 19646270 [patent_doc_number] => 20240420790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SELF-CALIBRATION IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/635869 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635869 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635869
SELF-CALIBRATION IN A MEMORY DEVICE Apr 14, 2024 Pending
Array ( [id] => 20036058 [patent_doc_number] => 20250174280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MEMORY DEVICES AND OPERATING METHODS THEREOF, AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/631424 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631424 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631424
MEMORY DEVICES AND OPERATING METHODS THEREOF, AND MEMORY SYSTEMS Apr 9, 2024 Pending
Array ( [id] => 20036058 [patent_doc_number] => 20250174280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MEMORY DEVICES AND OPERATING METHODS THEREOF, AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/631424 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631424 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631424
MEMORY DEVICES AND OPERATING METHODS THEREOF, AND MEMORY SYSTEMS Apr 9, 2024 Pending
Array ( [id] => 20036058 [patent_doc_number] => 20250174280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MEMORY DEVICES AND OPERATING METHODS THEREOF, AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/631424 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631424 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631424
MEMORY DEVICES AND OPERATING METHODS THEREOF, AND MEMORY SYSTEMS Apr 9, 2024 Pending
Array ( [id] => 19500120 [patent_doc_number] => 20240339138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => COMPUTE-IN-MEMORY CIRCUIT AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/629556 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629556 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629556
COMPUTE-IN-MEMORY CIRCUIT AND CONTROL METHOD THEREOF Apr 7, 2024 Pending
Array ( [id] => 19348933 [patent_doc_number] => 20240257897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => INTEGRATED CIRCUIT CHIP AND DIE TEST WITHOUT CELL ARRAY [patent_app_type] => utility [patent_app_number] => 18/623201 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623201 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623201
Integrated circuit chip and die test without cell array Mar 31, 2024 Issued
Array ( [id] => 19285364 [patent_doc_number] => 20240221841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTRIBUTIONS [patent_app_type] => utility [patent_app_number] => 18/604276 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604276 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604276
Fast bit erase for upper tail tightening of threshold voltage distributions Mar 12, 2024 Issued
Array ( [id] => 20118224 [patent_doc_number] => 12367939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Power management [patent_app_type] => utility [patent_app_number] => 18/583066 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 10060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583066 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583066
Power management Feb 20, 2024 Issued
Array ( [id] => 19221219 [patent_doc_number] => 20240185923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => TWO-PART PROGRAMMING OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/442437 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442437 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442437
TWO-PART PROGRAMMING OF MEMORY CELLS Feb 14, 2024 Pending
Array ( [id] => 19221219 [patent_doc_number] => 20240185923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => TWO-PART PROGRAMMING OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/442437 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442437 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442437
TWO-PART PROGRAMMING OF MEMORY CELLS Feb 14, 2024 Pending
Array ( [id] => 19221219 [patent_doc_number] => 20240185923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => TWO-PART PROGRAMMING OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/442437 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442437 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442437
TWO-PART PROGRAMMING OF MEMORY CELLS Feb 14, 2024 Pending
Array ( [id] => 19221192 [patent_doc_number] => 20240185896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => PSEUDO DUAL PORT MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/441089 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441089 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441089
Pseudo dual port memory devices Feb 13, 2024 Issued
Array ( [id] => 19221192 [patent_doc_number] => 20240185896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => PSEUDO DUAL PORT MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/441089 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441089 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441089
Pseudo dual port memory devices Feb 13, 2024 Issued
Array ( [id] => 19221192 [patent_doc_number] => 20240185896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => PSEUDO DUAL PORT MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/441089 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441089 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441089
Pseudo dual port memory devices Feb 13, 2024 Issued
Array ( [id] => 19205844 [patent_doc_number] => 20240177743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => METHODS FOR OPTIMIZING SEMICONDUCTOR DEVICE PLACEMENT ON A SUBSTRATE FOR IMPROVED PERFORMANCE, AND ASSOCIATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/431676 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431676 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/431676
METHODS FOR OPTIMIZING SEMICONDUCTOR DEVICE PLACEMENT ON A SUBSTRATE FOR IMPROVED PERFORMANCE, AND ASSOCIATED SYSTEMS AND METHODS Feb 1, 2024 Pending
Array ( [id] => 20317950 [patent_doc_number] => 12456505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems [patent_app_type] => utility [patent_app_number] => 18/424669 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424669 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424669
Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems Jan 25, 2024 Issued
Array ( [id] => 19175880 [patent_doc_number] => 20240161854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => READ COMMAND FAULT DETECTION IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/423059 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423059
READ COMMAND FAULT DETECTION IN A MEMORY SYSTEM Jan 24, 2024 Pending
Array ( [id] => 19116120 [patent_doc_number] => 20240127870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => CONFIGURING A HOST INTERFACE OF A MEMORY DEVICE BASED ON MODE OF OPERATION [patent_app_type] => utility [patent_app_number] => 18/393375 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18393375 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/393375
CONFIGURING A HOST INTERFACE OF A MEMORY DEVICE BASED ON MODE OF OPERATION Dec 20, 2023 Pending
Array ( [id] => 19285315 [patent_doc_number] => 20240221792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => REFLOW PROTECTION FOR A MODULE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/523151 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523151 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523151
REFLOW PROTECTION FOR A MODULE SEMICONDUCTOR DEVICE Nov 28, 2023 Pending
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