
Van Thu T. Nguyen
Examiner (ID: 947, Phone: (571)272-1881 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824, 2818 |
| Total Applications | 1819 |
| Issued Applications | 1543 |
| Pending Applications | 95 |
| Abandoned Applications | 210 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19886699
[patent_doc_number] => 12272424
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-08
[patent_title] => Reducing spurious write operations in a memory device
[patent_app_type] => utility
[patent_app_number] => 18/124489
[patent_app_country] => US
[patent_app_date] => 2023-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4280
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18124489
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/124489 | Reducing spurious write operations in a memory device | Mar 20, 2023 | Issued |
Array
(
[id] => 18958788
[patent_doc_number] => 20240047115
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => SWITCHING OF PERPENDICULARLY MAGNETIZED NANOMAGNETS WITH SPIN-ORBIT TORQUES IN THE ABSENCE OF EXTERNAL MAGNETIC FIELDS
[patent_app_type] => utility
[patent_app_number] => 18/123418
[patent_app_country] => US
[patent_app_date] => 2023-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2762
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123418
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/123418 | SWITCHING OF PERPENDICULARLY MAGNETIZED NANOMAGNETS WITH SPIN-ORBIT TORQUES IN THE ABSENCE OF EXTERNAL MAGNETIC FIELDS | Mar 19, 2023 | Abandoned |
Array
(
[id] => 19054454
[patent_doc_number] => 20240096423
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/177685
[patent_app_country] => US
[patent_app_date] => 2023-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20628
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177685
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/177685 | MEMORY SYSTEM | Mar 1, 2023 | Pending |
Array
(
[id] => 19054454
[patent_doc_number] => 20240096423
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/177685
[patent_app_country] => US
[patent_app_date] => 2023-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20628
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177685
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/177685 | MEMORY SYSTEM | Mar 1, 2023 | Pending |
Array
(
[id] => 19858051
[patent_doc_number] => 12260901
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-25
[patent_title] => Signal input buffer for effectively calibrating offset
[patent_app_type] => utility
[patent_app_number] => 18/099744
[patent_app_country] => US
[patent_app_date] => 2023-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 12175
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 551
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099744
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/099744 | Signal input buffer for effectively calibrating offset | Jan 19, 2023 | Issued |
Array
(
[id] => 18333153
[patent_doc_number] => 20230125101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-27
[patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/088046
[patent_app_country] => US
[patent_app_date] => 2022-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15704
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088046
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/088046 | Nonvolatile memory device and operation method of detecting defective memory cells | Dec 22, 2022 | Issued |
Array
(
[id] => 18455883
[patent_doc_number] => 20230197164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-22
[patent_title] => BIAS VOLTAGE SCHEMES DURING PRE-PROGRAMMING AND PROGRAMMING PHASES
[patent_app_type] => utility
[patent_app_number] => 18/076537
[patent_app_country] => US
[patent_app_date] => 2022-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11715
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076537
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/076537 | Bias voltage schemes during pre-programming and programming phases | Dec 6, 2022 | Issued |
Array
(
[id] => 18408681
[patent_doc_number] => 20230170034
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-01
[patent_title] => MEMORY DEVICE AND PROGRAM OPERATION THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/071026
[patent_app_country] => US
[patent_app_date] => 2022-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5874
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18071026
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/071026 | Memory device and program operation thereof to reduce capacitive coupling | Nov 28, 2022 | Issued |
Array
(
[id] => 19204615
[patent_doc_number] => 20240176514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-30
[patent_title] => SRAM COLUMN SLEEP CIRCUITS FOR LEAKAGE SAVINGS WITH RAPID WAKE
[patent_app_type] => utility
[patent_app_number] => 18/059360
[patent_app_country] => US
[patent_app_date] => 2022-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7532
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059360
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/059360 | SRAM COLUMN SLEEP CIRCUITS FOR LEAKAGE SAVINGS WITH RAPID WAKE | Nov 27, 2022 | Pending |
Array
(
[id] => 19507630
[patent_doc_number] => 12119059
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-15
[patent_title] => Write method for differential resistive memories
[patent_app_type] => utility
[patent_app_number] => 17/990723
[patent_app_country] => US
[patent_app_date] => 2022-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 7270
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17990723
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/990723 | Write method for differential resistive memories | Nov 19, 2022 | Issued |
Array
(
[id] => 19160844
[patent_doc_number] => 20240153551
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => Buried Metal Techniques for Memory Applications
[patent_app_type] => utility
[patent_app_number] => 17/980335
[patent_app_country] => US
[patent_app_date] => 2022-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8635
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17980335
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/980335 | Buried Metal Techniques for Memory Applications | Nov 2, 2022 | Pending |
Array
(
[id] => 19160844
[patent_doc_number] => 20240153551
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => Buried Metal Techniques for Memory Applications
[patent_app_type] => utility
[patent_app_number] => 17/980335
[patent_app_country] => US
[patent_app_date] => 2022-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8635
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17980335
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/980335 | Buried Metal Techniques for Memory Applications | Nov 2, 2022 | Pending |
Array
(
[id] => 18179255
[patent_doc_number] => 20230039984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => MEMORY DEVICES AND SYSTEMS WITH PARALLEL IMPEDANCE ADJUSTMENT CIRCUITRY AND METHODS FOR OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/970460
[patent_app_country] => US
[patent_app_date] => 2022-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9900
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17970460
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/970460 | Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same | Oct 19, 2022 | Issued |
Array
(
[id] => 18179255
[patent_doc_number] => 20230039984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-09
[patent_title] => MEMORY DEVICES AND SYSTEMS WITH PARALLEL IMPEDANCE ADJUSTMENT CIRCUITRY AND METHODS FOR OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/970460
[patent_app_country] => US
[patent_app_date] => 2022-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9900
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17970460
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/970460 | Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same | Oct 19, 2022 | Issued |
Array
(
[id] => 19733581
[patent_doc_number] => 12211581
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Memory device, memory system, and operation method of memory device
[patent_app_type] => utility
[patent_app_number] => 18/047614
[patent_app_country] => US
[patent_app_date] => 2022-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8337
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047614
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/047614 | Memory device, memory system, and operation method of memory device | Oct 17, 2022 | Issued |
Array
(
[id] => 18311560
[patent_doc_number] => 20230115460
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-13
[patent_title] => MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
[patent_app_type] => utility
[patent_app_number] => 17/961353
[patent_app_country] => US
[patent_app_date] => 2022-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13220
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 536
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961353
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/961353 | Memory device using dynamic flash memory cells | Oct 5, 2022 | Issued |
Array
(
[id] => 18311560
[patent_doc_number] => 20230115460
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-13
[patent_title] => MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
[patent_app_type] => utility
[patent_app_number] => 17/961353
[patent_app_country] => US
[patent_app_date] => 2022-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13220
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 536
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961353
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/961353 | Memory device using dynamic flash memory cells | Oct 5, 2022 | Issued |
Array
(
[id] => 19037838
[patent_doc_number] => 20240087653
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => Weight Calibration Check for Integrated Circuit Devices having Analog Inference Capability
[patent_app_type] => utility
[patent_app_number] => 17/940945
[patent_app_country] => US
[patent_app_date] => 2022-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25078
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940945
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/940945 | Weight calibration check for integrated circuit devices having analog inference capability | Sep 7, 2022 | Issued |
Array
(
[id] => 19022897
[patent_doc_number] => 20240079068
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-07
[patent_title] => DUAL-WAY SENSING SCHEME FOR BETTER NEIGHBORING WORD-LINE INTERFERENCE
[patent_app_type] => utility
[patent_app_number] => 17/939748
[patent_app_country] => US
[patent_app_date] => 2022-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11933
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939748
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/939748 | Dual-way sensing scheme for better neighboring word-line interference | Sep 6, 2022 | Issued |
Array
(
[id] => 19427949
[patent_doc_number] => 12087377
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Anti-fuse programming control circuit based on master-slave charge pump structure
[patent_app_type] => utility
[patent_app_number] => 17/903061
[patent_app_country] => US
[patent_app_date] => 2022-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5666
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903061
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/903061 | Anti-fuse programming control circuit based on master-slave charge pump structure | Sep 5, 2022 | Issued |