
Van Thu T. Nguyen
Examiner (ID: 18159)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2818, 2824 |
| Total Applications | 1817 |
| Issued Applications | 1534 |
| Pending Applications | 93 |
| Abandoned Applications | 210 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19733567
[patent_doc_number] => 12211567
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Memory system with verify operations of odd and even word lines
[patent_app_type] => utility
[patent_app_number] => 17/816836
[patent_app_country] => US
[patent_app_date] => 2022-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 40
[patent_no_of_words] => 23980
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 640
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816836
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/816836 | Memory system with verify operations of odd and even word lines | Aug 1, 2022 | Issued |
Array
(
[id] => 18009040
[patent_doc_number] => 20220367807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-17
[patent_title] => MEMORY DEVICE AND PROGRAMMING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/874298
[patent_app_country] => US
[patent_app_date] => 2022-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9755
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874298
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874298 | Memory device comprising heater of different heat conducting materials and programming method thereof | Jul 26, 2022 | Issued |
Array
(
[id] => 17994419
[patent_doc_number] => 20220360456
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => Systems and Methods for Providing Reliable Physically Unclonable Functions
[patent_app_type] => utility
[patent_app_number] => 17/873252
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6051
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873252
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/873252 | Systems and Methods for Providing Reliable Physically Unclonable Functions | Jul 25, 2022 | Pending |
Array
(
[id] => 20080599
[patent_doc_number] => 12354674
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Non-volatile memory power cycle protection mechanism
[patent_app_type] => utility
[patent_app_number] => 17/874100
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3482
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874100
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/874100 | Non-volatile memory power cycle protection mechanism | Jul 25, 2022 | Issued |
Array
(
[id] => 18926788
[patent_doc_number] => 20240029792
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => INCREASED PRECISION ANALOG CONTENT ADDRESSABLE MEMORIES
[patent_app_type] => utility
[patent_app_number] => 17/872882
[patent_app_country] => US
[patent_app_date] => 2022-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13518
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872882
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/872882 | Increased precision analog content addressable memories | Jul 24, 2022 | Issued |
Array
(
[id] => 17984504
[patent_doc_number] => 20220350541
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => MEMORY DEVICE INCLUDING INTERFACE CIRCUIT AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/867008
[patent_app_country] => US
[patent_app_date] => 2022-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7279
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867008
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/867008 | Memory device including interface circuit and method of operating the same | Jul 17, 2022 | Issued |
Array
(
[id] => 18585759
[patent_doc_number] => 20230268023
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-24
[patent_title] => Analog Signals Monitoring for Functional Safety
[patent_app_type] => utility
[patent_app_number] => 17/862917
[patent_app_country] => US
[patent_app_date] => 2022-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8112
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862917
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/862917 | Analog signals monitoring for functional safety | Jul 11, 2022 | Issued |
Array
(
[id] => 19523795
[patent_doc_number] => 12125533
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-22
[patent_title] => Non-volatile memory device readable only a predetermined number of times
[patent_app_type] => utility
[patent_app_number] => 17/812122
[patent_app_country] => US
[patent_app_date] => 2022-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 19
[patent_no_of_words] => 5747
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812122
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/812122 | Non-volatile memory device readable only a predetermined number of times | Jul 11, 2022 | Issued |
Array
(
[id] => 18143714
[patent_doc_number] => 20230017565
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => METHOD OF READING A MULTI-LEVEL RRAM
[patent_app_type] => utility
[patent_app_number] => 17/811341
[patent_app_country] => US
[patent_app_date] => 2022-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7883
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 311
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17811341
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/811341 | METHOD OF READING A MULTI-LEVEL RRAM | Jul 7, 2022 | Abandoned |
Array
(
[id] => 18882641
[patent_doc_number] => 20240006010
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-04
[patent_title] => Storage System and Method for Proactive Die Retirement by Fatal Wordline Leakage Detection
[patent_app_type] => utility
[patent_app_number] => 17/856073
[patent_app_country] => US
[patent_app_date] => 2022-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5858
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856073
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/856073 | Storage system and method for proactive die retirement by fatal wordline leakage detection | Jun 30, 2022 | Issued |
Array
(
[id] => 19168242
[patent_doc_number] => 11984153
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-14
[patent_title] => Memory device
[patent_app_type] => utility
[patent_app_number] => 17/855743
[patent_app_country] => US
[patent_app_date] => 2022-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2916
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855743
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/855743 | Memory device | Jun 29, 2022 | Issued |
Array
(
[id] => 18068950
[patent_doc_number] => 20220400038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-15
[patent_title] => MULTIPLEXING DISTINCT SIGNALS ON A SINGLE PIN OF A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/851533
[patent_app_country] => US
[patent_app_date] => 2022-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 36359
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851533
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/851533 | MULTIPLEXING DISTINCT SIGNALS ON A SINGLE PIN OF A MEMORY DEVICE | Jun 27, 2022 | Pending |
Array
(
[id] => 17932971
[patent_doc_number] => 20220328097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => BOOST SCHEMES FOR WRITE ASSIST
[patent_app_type] => utility
[patent_app_number] => 17/850354
[patent_app_country] => US
[patent_app_date] => 2022-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7900
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850354
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/850354 | BOOST SCHEMES FOR WRITE ASSIST | Jun 26, 2022 | Pending |
Array
(
[id] => 18423674
[patent_doc_number] => 20230178138
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-08
[patent_title] => READ CLOCK START AND STOP FOR SYNCHRONOUS MEMORIES
[patent_app_type] => utility
[patent_app_number] => 17/850499
[patent_app_country] => US
[patent_app_date] => 2022-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5400
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850499
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/850499 | Read clock start and stop for synchronous memories | Jun 26, 2022 | Issued |
Array
(
[id] => 18585712
[patent_doc_number] => 20230267976
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-24
[patent_title] => MEMORY CIRCUIT, DATA TRANSMISSION CIRCUIT, AND MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/807027
[patent_app_country] => US
[patent_app_date] => 2022-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8759
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807027
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/807027 | MEMORY CIRCUIT, DATA TRANSMISSION CIRCUIT, AND MEMORY | Jun 14, 2022 | Abandoned |
Array
(
[id] => 18439679
[patent_doc_number] => 20230186974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-15
[patent_title] => MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/806073
[patent_app_country] => US
[patent_app_date] => 2022-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5984
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806073
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/806073 | MEMORY | Jun 7, 2022 | Abandoned |
Array
(
[id] => 18168142
[patent_doc_number] => 20230034752
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-02
[patent_title] => FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTRIBUTIONS
[patent_app_type] => utility
[patent_app_number] => 17/833466
[patent_app_country] => US
[patent_app_date] => 2022-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16086
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833466
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/833466 | Fast bit erase for upper tail tightening of threshold voltage distributions | Jun 5, 2022 | Issued |
Array
(
[id] => 18848502
[patent_doc_number] => 20230410906
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => DUMMY CELL RESISTANCE TUNING IN NAND STRINGS
[patent_app_type] => utility
[patent_app_number] => 17/824143
[patent_app_country] => US
[patent_app_date] => 2022-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14569
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824143
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/824143 | Dummy cell resistance tuning in NAND strings | May 24, 2022 | Issued |
Array
(
[id] => 18812243
[patent_doc_number] => 20230386580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING
[patent_app_type] => utility
[patent_app_number] => 17/824350
[patent_app_country] => US
[patent_app_date] => 2022-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11673
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824350
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/824350 | Method to optimize first read versus second read margin by switching boost timing | May 24, 2022 | Issued |
Array
(
[id] => 18669680
[patent_doc_number] => 11776590
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-03
[patent_title] => On-the-fly programming and verifying method for memory cells based on counters and ECC feedback
[patent_app_type] => utility
[patent_app_number] => 17/748866
[patent_app_country] => US
[patent_app_date] => 2022-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 14866
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748866
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/748866 | On-the-fly programming and verifying method for memory cells based on counters and ECC feedback | May 18, 2022 | Issued |