Search

Van Thu T. Nguyen

Examiner (ID: 947, Phone: (571)272-1881 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824, 2818
Total Applications
1819
Issued Applications
1543
Pending Applications
95
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18068950 [patent_doc_number] => 20220400038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => MULTIPLEXING DISTINCT SIGNALS ON A SINGLE PIN OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/851533 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851533
MULTIPLEXING DISTINCT SIGNALS ON A SINGLE PIN OF A MEMORY DEVICE Jun 27, 2022 Pending
Array ( [id] => 17932971 [patent_doc_number] => 20220328097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => BOOST SCHEMES FOR WRITE ASSIST [patent_app_type] => utility [patent_app_number] => 17/850354 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850354
BOOST SCHEMES FOR WRITE ASSIST Jun 26, 2022 Pending
Array ( [id] => 18423674 [patent_doc_number] => 20230178138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => READ CLOCK START AND STOP FOR SYNCHRONOUS MEMORIES [patent_app_type] => utility [patent_app_number] => 17/850499 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850499
Read clock start and stop for synchronous memories Jun 26, 2022 Issued
Array ( [id] => 18585712 [patent_doc_number] => 20230267976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => MEMORY CIRCUIT, DATA TRANSMISSION CIRCUIT, AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/807027 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807027 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/807027
MEMORY CIRCUIT, DATA TRANSMISSION CIRCUIT, AND MEMORY Jun 14, 2022 Abandoned
Array ( [id] => 18439679 [patent_doc_number] => 20230186974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => MEMORY [patent_app_type] => utility [patent_app_number] => 17/806073 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806073 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806073
MEMORY Jun 7, 2022 Abandoned
Array ( [id] => 18168142 [patent_doc_number] => 20230034752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTRIBUTIONS [patent_app_type] => utility [patent_app_number] => 17/833466 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833466 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833466
Fast bit erase for upper tail tightening of threshold voltage distributions Jun 5, 2022 Issued
Array ( [id] => 18848502 [patent_doc_number] => 20230410906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => DUMMY CELL RESISTANCE TUNING IN NAND STRINGS [patent_app_type] => utility [patent_app_number] => 17/824143 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824143 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824143
Dummy cell resistance tuning in NAND strings May 24, 2022 Issued
Array ( [id] => 18812243 [patent_doc_number] => 20230386580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING [patent_app_type] => utility [patent_app_number] => 17/824350 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824350
Method to optimize first read versus second read margin by switching boost timing May 24, 2022 Issued
Array ( [id] => 18669680 [patent_doc_number] => 11776590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => On-the-fly programming and verifying method for memory cells based on counters and ECC feedback [patent_app_type] => utility [patent_app_number] => 17/748866 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 14866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748866 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748866
On-the-fly programming and verifying method for memory cells based on counters and ECC feedback May 18, 2022 Issued
Array ( [id] => 19341266 [patent_doc_number] => 12051461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Bit line sense amplifier and semiconductor memory device having the same [patent_app_type] => utility [patent_app_number] => 17/748357 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9023 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748357 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748357
Bit line sense amplifier and semiconductor memory device having the same May 18, 2022 Issued
Array ( [id] => 18774016 [patent_doc_number] => 20230368846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => MEMORY CELL GROUP READ WITH COMPENSATION FOR DIFFERENT PROGRAMMING SPEEDS [patent_app_type] => utility [patent_app_number] => 17/740429 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17740429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/740429
Memory cell group read with compensation for different programming speeds May 9, 2022 Issued
Array ( [id] => 19046483 [patent_doc_number] => 11935602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Power management [patent_app_type] => utility [patent_app_number] => 17/738126 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 15096 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/738126
Power management May 5, 2022 Issued
Array ( [id] => 19079279 [patent_doc_number] => 11948654 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-02 [patent_title] => Distributed phased SRAM repair for systems on a chip [patent_app_type] => utility [patent_app_number] => 17/662178 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662178 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662178
Distributed phased SRAM repair for systems on a chip May 4, 2022 Issued
Array ( [id] => 18040234 [patent_doc_number] => 20220384451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MEMORY STRUCTURE AND MEMORY LAYOUT [patent_app_type] => utility [patent_app_number] => 17/661321 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/661321
MEMORY STRUCTURE AND MEMORY LAYOUT Apr 28, 2022 Abandoned
Array ( [id] => 19720125 [patent_doc_number] => 12205668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/722805 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 9394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722805
Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same Apr 17, 2022 Issued
Array ( [id] => 18857062 [patent_doc_number] => 11854653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Signal masking circuit and semiconductor memory [patent_app_type] => utility [patent_app_number] => 17/659325 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 11914 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17659325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/659325
Signal masking circuit and semiconductor memory Apr 13, 2022 Issued
Array ( [id] => 18623540 [patent_doc_number] => 11756593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Memory control circuit, information processing system, and memory control method [patent_app_type] => utility [patent_app_number] => 17/718796 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8326 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718796
Memory control circuit, information processing system, and memory control method Apr 11, 2022 Issued
Array ( [id] => 19733582 [patent_doc_number] => 12211582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Signed and binary weighted computation for an in-memory computation system [patent_app_type] => utility [patent_app_number] => 17/718755 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 15893 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718755
Signed and binary weighted computation for an in-memory computation system Apr 11, 2022 Issued
Array ( [id] => 18229672 [patent_doc_number] => 20230068666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => METHODS FOR OPTIMIZING SEMICONDUCTOR DEVICE PLACEMENT ON A SUBSTRATE FOR IMPROVED PERFORMANCE, AND ASSOCIATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/718200 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718200
Methods for optimizing semiconductor device placement on a substrate for improved performance, and associated systems and methods Apr 10, 2022 Issued
Array ( [id] => 17886142 [patent_doc_number] => 20220301619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => READING A MULTI-LEVEL MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/716740 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/716740
Reading a multi-level memory cell Apr 7, 2022 Issued
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