Search

Vi N Tran

Examiner (ID: 177)

Most Active Art Unit
2117
Art Unit(s)
2117
Total Applications
96
Issued Applications
17
Pending Applications
48
Abandoned Applications
31
Applications
StatisticsSubscription-Only

Applications

Application numberTitle of the applicationFiling DateStatus
07/901575 OBJECT RECOGNITION APPARATUS USING A HIERARCHICAL NETWORK OF RECOGNITION UNITS Jun 18, 1992 Abandoned
Array ( [id] => 3423625 [patent_doc_number] => 05434520 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Clocking systems and methods for pipelined self-timed dynamic logic circuits' [patent_app_type] => 1 [patent_app_number] => 7/885800 [patent_app_country] => US [patent_app_date] => 1992-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14791 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434520.pdf [firstpage_image] =>[orig_patent_app_number] => 885800 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/885800 		Clocking systems and methods for pipelined self-timed dynamic logic circuits May 18, 1992 Issued
07/885086 AN APPARATUS WHICH ALLOWS DATA SHARING AMONGST COMPUTER PROGRAMS FROM DIFFERENT PROGRAM ENVIRONMENTS May 17, 1992 Abandoned
07/883011 INFORMATION PROCESSING SECTION AND SYSTEM FOR OPERATION A PLURALITY OF VECTOR PIPELINE SETS IN TWO DIFFERENT MODES May 13, 1992 Abandoned
07/883584 INTERACTIVELY DISPLAYING SIGNAL INFORMATION DURING COMPUTER SIMULATION OF AN ELECTRICAL CIRCUIT May 13, 1992 Abandoned
07/882593 SYSTEM FOR SUPPORTING A CONVERSION BETWEEN ABSTRACT SYNTAX AND TRANSFER SYNTAX May 12, 1992 Abandoned
07/881597 A PARALLEL DIAGONAL-FOLD ARRAY PROCESSOR May 11, 1992 Abandoned
07/881594 SCALABLE PARALLEL GROUP PARTITIONED DIAGONAL-FOLD SWITCHING TREE COMPUTING APPARATUS May 11, 1992 Abandoned
Array ( [id] => 3626949 [patent_doc_number] => 05511213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Associative memory processor architecture for the efficient execution of parsing algorithms for natural language processing and pattern recognition' [patent_app_type] => 1 [patent_app_number] => 7/880711 [patent_app_country] => US [patent_app_date] => 1992-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8665 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/511/05511213.pdf [firstpage_image] =>[orig_patent_app_number] => 880711 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/880711 		Associative memory processor architecture for the efficient execution of parsing algorithms for natural language processing and pattern recognition May 7, 1992 Issued
Array ( [id] => 3661455 [patent_doc_number] => 05606675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Data processor for invalidating prefetched instruction or branch history information' [patent_app_type] => 1 [patent_app_number] => 7/873525 [patent_app_country] => US [patent_app_date] => 1992-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1574 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606675.pdf [firstpage_image] =>[orig_patent_app_number] => 873525 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/873525 		Data processor for invalidating prefetched instruction or branch history information Apr 20, 1992 Issued
07/870024 SYSTEM AND METHOD FOR MAPPING DIRECTLY ACCESSIBLE MAGNETIC DASD STORAGE TO FIXED BLOCK OPTICAL STORAGE Apr 16, 1992 Abandoned
07/859084 MICROSEQUENCER ALLOWING A SEQUENCE OF CODITIONAL JUMPS WITHOUT REQUIRING THE INSERTION OF NOP OR OTHER INSTRUCTIONS Mar 26, 1992 Abandoned
07/857545 METHOD AND SYSTEM FOR GENERATING A PROGRAM TO FACILITATE REARRANGEMENT OF ADDRESS BITS AMONG ADDRESSES IN A MASSIVELY PARALLEL PROCESSOR SYSTEM Mar 24, 1992 Abandoned
Array ( [id] => 3133638 [patent_doc_number] => 05450598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Finite state machine data storage where data transition is accomplished without the use of pointers' [patent_app_type] => 1 [patent_app_number] => 7/855129 [patent_app_country] => US [patent_app_date] => 1992-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 14115 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450598.pdf [firstpage_image] =>[orig_patent_app_number] => 855129 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/855129 		Finite state machine data storage where data transition is accomplished without the use of pointers Mar 17, 1992 Issued
07/826907 A SIMULTANEOUS PARITY GENERATING/READING CIRCUIT FOR MASSIVELY PARALLEL PROCESSING SYSTEMS Jan 23, 1992 Abandoned
07/822502 MICROCOMPUTER SYSTEM Jan 16, 1992 Abandoned
07/820119 METHOD AND SYSTEM FOR MEASURING BRANCH PASSING COVERAGE IN MICROPROGRAM BY USE OF MEMORIES FOR HOLDING PROGRAM ADDRESSES OF INSTRUCTIONS CURRENTLY AND LATEST EXECUTED FOR USE IN LOGIC SIMULATOR Jan 12, 1992 Abandoned
07/819023 EFFICIENT DATA ALLOCATION CONVERSION METHOD FOR A MULTIPROCESSOR COMPUTER SYSTEM Jan 9, 1992 Abandoned
Array ( [id] => 3502020 [patent_doc_number] => 05471632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'System for transferring data between a processor and a system bus including a device which packs, unpacks, or buffers data blocks being transferred' [patent_app_type] => 1 [patent_app_number] => 7/819468 [patent_app_country] => US [patent_app_date] => 1992-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 22827 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471632.pdf [firstpage_image] =>[orig_patent_app_number] => 819468 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/819468 		System for transferring data between a processor and a system bus including a device which packs, unpacks, or buffers data blocks being transferred Jan 9, 1992 Issued
07/818028 NEW HIERARCHICAL INTERCONNECTION NETWORKDS FOR PARALLEL PROCESSING Jan 6, 1992 Abandoned
Menu