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Examiner (ID: 177)

Most Active Art Unit
2117
Art Unit(s)
2117
Total Applications
96
Issued Applications
17
Pending Applications
48
Abandoned Applications
31

Applications

Application numberTitle of the applicationFiling DateStatus
07/686280 STATE MACHINE BUS CONTROLLER Apr 14, 1991 Abandoned
07/678711 PIPELINE INFORMATION PROCESSING CIRCUIT FOR FLOATING POINT OPERATIONS Mar 31, 1991 Abandoned
07/676604 BIDIRECTIONAL PROGRAMMABLE I/O DRIVER ARRAY Mar 27, 1991 Abandoned
Array ( [id] => 3129754 [patent_doc_number] => 05410717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Removable function card for a programmable controller processor' [patent_app_type] => 1 [patent_app_number] => 7/674826 [patent_app_country] => US [patent_app_date] => 1991-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9588 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410717.pdf [firstpage_image] =>[orig_patent_app_number] => 674826 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/674826
Removable function card for a programmable controller processor Mar 21, 1991 Issued
07/669824 ALLOCATION OF RESOURCES OF A PIPELINED PROCESSOR BY CLOCK PHASE FOR PARALLEL EXECUTION OF MULTIPLE PROCESSES Mar 14, 1991 Abandoned
Array ( [id] => 3065402 [patent_doc_number] => 05307504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'System and method for preserving instruction granularity when translating program code from a computer having a first architecture to a computer having a second reduced architecture during the occurrence of interrupts due to asynchronous events' [patent_app_type] => 1 [patent_app_number] => 7/666025 [patent_app_country] => US [patent_app_date] => 1991-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5530 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/307/05307504.pdf [firstpage_image] =>[orig_patent_app_number] => 666025 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/666025
System and method for preserving instruction granularity when translating program code from a computer having a first architecture to a computer having a second reduced architecture during the occurrence of interrupts due to asynchronous events Mar 6, 1991 Issued
Array ( [id] => 3437489 [patent_doc_number] => 05404454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Method for interleaving computer disk data input-out transfers with permuted buffer addressing' [patent_app_type] => 1 [patent_app_number] => 7/662533 [patent_app_country] => US [patent_app_date] => 1991-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7110 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404454.pdf [firstpage_image] =>[orig_patent_app_number] => 662533 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/662533
Method for interleaving computer disk data input-out transfers with permuted buffer addressing Feb 27, 1991 Issued
Array ( [id] => 3701835 [patent_doc_number] => 05604885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Apparatus and method enabling a computer to transfer control between two program segments that call one another but operate in different modes' [patent_app_type] => 1 [patent_app_number] => 7/649624 [patent_app_country] => US [patent_app_date] => 1991-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5692 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604885.pdf [firstpage_image] =>[orig_patent_app_number] => 649624 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/649624
Apparatus and method enabling a computer to transfer control between two program segments that call one another but operate in different modes Jan 31, 1991 Issued
07/648113 DUAL PATH COMPUTER CONTROL SYSTEM Jan 30, 1991 Abandoned
07/647936 PRIORITY ENCODER Jan 29, 1991 Abandoned
Array ( [id] => 3503325 [patent_doc_number] => 05440750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Information processing system capable of executing a single instruction for watching and waiting for writing of information for synchronization by another processor' [patent_app_type] => 1 [patent_app_number] => 7/643121 [patent_app_country] => US [patent_app_date] => 1991-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 19683 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440750.pdf [firstpage_image] =>[orig_patent_app_number] => 643121 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/643121
Information processing system capable of executing a single instruction for watching and waiting for writing of information for synchronization by another processor Jan 17, 1991 Issued
07/624026 DATA PROCESSING HAVING INCIRCUIT EMULATION FUNCTION Dec 6, 1990 Abandoned
Array ( [id] => 3472459 [patent_doc_number] => 05442795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'System and method for viewing icon contents on a video display' [patent_app_type] => 1 [patent_app_number] => 7/616812 [patent_app_country] => US [patent_app_date] => 1990-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9867 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442795.pdf [firstpage_image] =>[orig_patent_app_number] => 616812 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/616812
System and method for viewing icon contents on a video display Nov 18, 1990 Issued
07/611019 METHOD FOR TESTING DESIGN TIMING PARAMETERS USING A TIMING SHELL GENERATOR Nov 8, 1990 Abandoned
07/580417 MULTIPLE SEQUENTIALLY TRANSFERRABLE STACKPOINTERS IN A DATA PROCESSOR HAVING A PIPELINING SYSTEM Sep 9, 1990 Abandoned
Array ( [id] => 3487387 [patent_doc_number] => 05428802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Method and apparatus for executing critical disk access commands' [patent_app_type] => 1 [patent_app_number] => 7/524206 [patent_app_country] => US [patent_app_date] => 1990-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5157 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/428/05428802.pdf [firstpage_image] =>[orig_patent_app_number] => 524206 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/524206
Method and apparatus for executing critical disk access commands May 15, 1990 Issued
Array ( [id] => 3556845 [patent_doc_number] => 05555425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Multi-master bus arbitration system in which the address and data lines of the bus may be separately granted to individual masters' [patent_app_type] => 1 [patent_app_number] => 7/490003 [patent_app_country] => US [patent_app_date] => 1990-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5746 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555425.pdf [firstpage_image] =>[orig_patent_app_number] => 490003 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/490003
Multi-master bus arbitration system in which the address and data lines of the bus may be separately granted to individual masters Mar 6, 1990 Issued
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