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Vi N Tran

Examiner (ID: 177)

Most Active Art Unit
2117
Art Unit(s)
2117
Total Applications
96
Issued Applications
17
Pending Applications
48
Abandoned Applications
31

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3567080 [patent_doc_number] => 05574936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Access control mechanism controlling access to and logical purging of access register translation lookaside buffer (ALB) in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/378082 [patent_app_country] => US [patent_app_date] => 1995-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 18560 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574936.pdf [firstpage_image] =>[orig_patent_app_number] => 378082 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/378082
Access control mechanism controlling access to and logical purging of access register translation lookaside buffer (ALB) in a computer system Jan 24, 1995 Issued
Array ( [id] => 3622165 [patent_doc_number] => 05590362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Database engine predicate evaluator' [patent_app_type] => 1 [patent_app_number] => 8/378985 [patent_app_country] => US [patent_app_date] => 1995-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 21802 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590362.pdf [firstpage_image] =>[orig_patent_app_number] => 378985 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/378985
Database engine predicate evaluator Jan 23, 1995 Issued
Array ( [id] => 3526936 [patent_doc_number] => 05513371 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressible nodes based on address bit permutations' [patent_app_type] => 1 [patent_app_number] => 8/378981 [patent_app_country] => US [patent_app_date] => 1995-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15370 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 422 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513371.pdf [firstpage_image] =>[orig_patent_app_number] => 378981 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/378981
Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressible nodes based on address bit permutations Jan 23, 1995 Issued
Array ( [id] => 3661906 [patent_doc_number] => 05606711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Apparatus and method for providing multiple output signals from a single programming line group' [patent_app_type] => 1 [patent_app_number] => 8/376479 [patent_app_country] => US [patent_app_date] => 1995-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2015 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606711.pdf [firstpage_image] =>[orig_patent_app_number] => 376479 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/376479
Apparatus and method for providing multiple output signals from a single programming line group Jan 19, 1995 Issued
Array ( [id] => 3627083 [patent_doc_number] => 05511222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Priority encoder' [patent_app_type] => 1 [patent_app_number] => 8/375009 [patent_app_country] => US [patent_app_date] => 1995-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4423 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/511/05511222.pdf [firstpage_image] =>[orig_patent_app_number] => 375009 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/375009
Priority encoder Jan 17, 1995 Issued
Array ( [id] => 3842313 [patent_doc_number] => 05784630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory' [patent_app_type] => 1 [patent_app_number] => 8/367928 [patent_app_country] => US [patent_app_date] => 1995-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 23815 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784630.pdf [firstpage_image] =>[orig_patent_app_number] => 367928 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/367928
Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory Jan 2, 1995 Issued
08/364186 CONNECTION-ORIENTED NETWORK USING DISTRIBUTED NETWORK RESOURCES AND PREDETERMINED VPIS FOR FAST VC ESTABLISHMENT Dec 26, 1994 Abandoned
Array ( [id] => 3674346 [patent_doc_number] => 05649227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'System for supporting a conversion between abstract syntax and transfer syntax' [patent_app_type] => 1 [patent_app_number] => 8/364427 [patent_app_country] => US [patent_app_date] => 1994-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1865 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649227.pdf [firstpage_image] =>[orig_patent_app_number] => 364427 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/364427
System for supporting a conversion between abstract syntax and transfer syntax Dec 26, 1994 Issued
Array ( [id] => 3919627 [patent_doc_number] => 05752060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'File access scheme in distributed data processing system' [patent_app_type] => 1 [patent_app_number] => 8/364385 [patent_app_country] => US [patent_app_date] => 1994-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5166 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 443 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752060.pdf [firstpage_image] =>[orig_patent_app_number] => 364385 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/364385
File access scheme in distributed data processing system Dec 22, 1994 Issued
Array ( [id] => 3622149 [patent_doc_number] => 05590361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Microprocessor having an effective BiCMOS extra multiple input complex logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/364406 [patent_app_country] => US [patent_app_date] => 1994-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5099 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590361.pdf [firstpage_image] =>[orig_patent_app_number] => 364406 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/364406
Microprocessor having an effective BiCMOS extra multiple input complex logic circuit Dec 22, 1994 Issued
Array ( [id] => 3518758 [patent_doc_number] => 05515527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Method and system for measuring branch passing coverage in microprogram by use of memories for holding program addresses of instructions currently and latest executed for use in logic simulator' [patent_app_type] => 1 [patent_app_number] => 8/361703 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4527 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 488 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/515/05515527.pdf [firstpage_image] =>[orig_patent_app_number] => 361703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/361703
Method and system for measuring branch passing coverage in microprogram by use of memories for holding program addresses of instructions currently and latest executed for use in logic simulator Dec 21, 1994 Issued
08/363107 A COMPUTER SYSTEM HAVING A MINIMUM LATENCY CACHE WHICH STORES INSTRUCTIONS DECODED TO DETERMINE CLASS, BRANCH PREDICTION AND NEXT FETCH ADDRESS PREDICTION INFORMATION Dec 21, 1994 Abandoned
Array ( [id] => 3622134 [patent_doc_number] => 05590360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Apparatus and method for gathering and entering data requirements from multiple users in the building of process models and data models' [patent_app_type] => 1 [patent_app_number] => 8/360195 [patent_app_country] => US [patent_app_date] => 1994-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 7544 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590360.pdf [firstpage_image] =>[orig_patent_app_number] => 360195 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/360195
Apparatus and method for gathering and entering data requirements from multiple users in the building of process models and data models Dec 19, 1994 Issued
Array ( [id] => 3735001 [patent_doc_number] => 05682544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Massively parallel diagonal-fold tree array processor' [patent_app_type] => 1 [patent_app_number] => 8/359250 [patent_app_country] => US [patent_app_date] => 1994-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7819 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682544.pdf [firstpage_image] =>[orig_patent_app_number] => 359250 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/359250
Massively parallel diagonal-fold tree array processor Dec 18, 1994 Issued
Array ( [id] => 3735583 [patent_doc_number] => 05701412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Telecommunications service control method in intelligent network' [patent_app_type] => 1 [patent_app_number] => 8/355509 [patent_app_country] => US [patent_app_date] => 1994-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6576 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701412.pdf [firstpage_image] =>[orig_patent_app_number] => 355509 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/355509
Telecommunications service control method in intelligent network Dec 13, 1994 Issued
Array ( [id] => 3782466 [patent_doc_number] => 05850518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Access-method-independent exchange' [patent_app_type] => 1 [patent_app_number] => 8/353905 [patent_app_country] => US [patent_app_date] => 1994-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 154 [patent_no_of_words] => 26633 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850518.pdf [firstpage_image] =>[orig_patent_app_number] => 353905 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/353905
Access-method-independent exchange Dec 11, 1994 Issued
Array ( [id] => 3672541 [patent_doc_number] => 05649108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Combined progressive and source routing control for connection-oriented communications networks' [patent_app_type] => 1 [patent_app_number] => 8/351073 [patent_app_country] => US [patent_app_date] => 1994-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 8097 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649108.pdf [firstpage_image] =>[orig_patent_app_number] => 351073 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/351073
Combined progressive and source routing control for connection-oriented communications networks Nov 29, 1994 Issued
Array ( [id] => 3588858 [patent_doc_number] => 05524222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Microsequencer allowing a sequence of conditional jumps without requiring the insertion of NOP or other instructions' [patent_app_type] => 1 [patent_app_number] => 8/343277 [patent_app_country] => US [patent_app_date] => 1994-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3639 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/524/05524222.pdf [firstpage_image] =>[orig_patent_app_number] => 343277 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/343277
Microsequencer allowing a sequence of conditional jumps without requiring the insertion of NOP or other instructions Nov 21, 1994 Issued
Array ( [id] => 3601825 [patent_doc_number] => 05517663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Animated user interface for computer program creation, control and execution' [patent_app_type] => 1 [patent_app_number] => 8/336557 [patent_app_country] => US [patent_app_date] => 1994-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8249 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517663.pdf [firstpage_image] =>[orig_patent_app_number] => 336557 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/336557
Animated user interface for computer program creation, control and execution Nov 8, 1994 Issued
Array ( [id] => 3633518 [patent_doc_number] => 05615356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Method and apparatus for interactively displaying signal information during computer simulation of an electrical circuit' [patent_app_type] => 1 [patent_app_number] => 8/334769 [patent_app_country] => US [patent_app_date] => 1994-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3439 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615356.pdf [firstpage_image] =>[orig_patent_app_number] => 334769 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/334769
Method and apparatus for interactively displaying signal information during computer simulation of an electrical circuit Nov 3, 1994 Issued
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