
Vibol Tan
Examiner (ID: 7718, Phone: (571)272-1811 , Office: P/2844 )
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2844, 2819 |
| Total Applications | 2718 |
| Issued Applications | 2530 |
| Pending Applications | 32 |
| Abandoned Applications | 163 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1452522
[patent_doc_number] => 06370674
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[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'Process for evaluating the performance of very high scale integrated circuits'
[patent_app_type] => B1
[patent_app_number] => 09/233939
[patent_app_country] => US
[patent_app_date] => 1999-01-20
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[pdf_file] => patents/06/370/06370674.pdf
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Array
(
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[patent_issue_date] => 2002-01-22
[patent_title] => 'Rule-driven method and system for editing physical integrated circuit layouts'
[patent_app_type] => B1
[patent_app_number] => 09/232467
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[patent_app_date] => 1999-01-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/232467 | Rule-driven method and system for editing physical integrated circuit layouts | Jan 14, 1999 | Issued |
Array
(
[id] => 4423856
[patent_doc_number] => 06311313
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-30
[patent_title] => 'X-Y grid tree clock distribution network with tunable tree and grid networks'
[patent_app_type] => 1
[patent_app_number] => 9/222141
[patent_app_country] => US
[patent_app_date] => 1998-12-29
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[patent_drawing_sheets_cnt] => 12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/222141 | X-Y grid tree clock distribution network with tunable tree and grid networks | Dec 28, 1998 | Issued |
Array
(
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[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-28
[patent_title] => 'Method and system for breaking complex Boolean networks'
[patent_app_type] => B1
[patent_app_number] => 09/216357
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/216357 | Method and system for breaking complex Boolean networks | Dec 17, 1998 | Issued |
Array
(
[id] => 1501809
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[patent_issue_date] => 2002-06-11
[patent_title] => 'Method and apparatus to optimize power wiring layout and generate wiring layout data for a semiconductor integrated circuit'
[patent_app_type] => B1
[patent_app_number] => 09/215239
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/215239 | Method and apparatus to optimize power wiring layout and generate wiring layout data for a semiconductor integrated circuit | Dec 17, 1998 | Issued |
Array
(
[id] => 1587633
[patent_doc_number] => 06425110
[patent_country] => US
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[patent_issue_date] => 2002-07-23
[patent_title] => 'Incremental design tuning and decision mediator'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/213675 | Incremental design tuning and decision mediator | Dec 16, 1998 | Issued |
Array
(
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[patent_doc_number] => 06460166
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[patent_title] => 'System and method for restructuring of logic circuitry'
[patent_app_type] => B1
[patent_app_number] => 09/213322
[patent_app_country] => US
[patent_app_date] => 1998-12-16
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[firstpage_image] =>[orig_patent_app_number] => 09213322
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/213322 | System and method for restructuring of logic circuitry | Dec 15, 1998 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Method and system for synthesizing operational amplifiers for amplifying systems with minimal total harmonic distortion'
[patent_app_type] => 1
[patent_app_number] => 9/206747
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[patent_app_date] => 1998-12-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/206747 | Method and system for synthesizing operational amplifiers for amplifying systems with minimal total harmonic distortion | Dec 6, 1998 | Issued |
Array
(
[id] => 4374915
[patent_doc_number] => 06292927
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Reduction of process antenna effects in integrated circuits'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/207159 | Reduction of process antenna effects in integrated circuits | Dec 6, 1998 | Issued |
Array
(
[id] => 1549888
[patent_doc_number] => 06374396
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[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Correction of field effects in photolithography'
[patent_app_type] => B1
[patent_app_number] => 09/205896
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205896 | Correction of field effects in photolithography | Dec 3, 1998 | Issued |
Array
(
[id] => 4412975
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[patent_issue_date] => 2001-10-02
[patent_title] => 'Apparatus and method for inhibiting pattern distortions to correct pattern data in a semiconductor device'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/204281 | Apparatus and method for inhibiting pattern distortions to correct pattern data in a semiconductor device | Dec 2, 1998 | Issued |
Array
(
[id] => 4424405
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[patent_issue_date] => 2001-10-09
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Array
(
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[patent_title] => 'Method for implementing wide gates and tristate buffers using FPGA carry logic'
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Array
(
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[patent_title] => 'Systematic approach for regularity extraction'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/187543 | Systematic approach for regularity extraction | Nov 5, 1998 | Issued |
| 09/192177 | METHOD AND APPARATUS FOR GENERATING PACKAGE GEOMETRIES | Oct 29, 1998 | Abandoned |
Array
(
[id] => 4380534
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Array
(
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[patent_title] => 'Zero hold time circuit for high speed bus applications'
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/162215 | Spacing violation checker | Sep 27, 1998 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/157387 | Automatic routing method | Sep 20, 1998 | Issued |