Search

Vibol Tan

Examiner (ID: 7718, Phone: (571)272-1811 , Office: P/2844 )

Most Active Art Unit
2819
Art Unit(s)
2844, 2819
Total Applications
2718
Issued Applications
2530
Pending Applications
32
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1452522 [patent_doc_number] => 06370674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Process for evaluating the performance of very high scale integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/233939 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8353 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370674.pdf [firstpage_image] =>[orig_patent_app_number] => 09233939 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233939
Process for evaluating the performance of very high scale integrated circuits Jan 19, 1999 Issued
Array ( [id] => 1434076 [patent_doc_number] => 06341366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Rule-driven method and system for editing physical integrated circuit layouts' [patent_app_type] => B1 [patent_app_number] => 09/232467 [patent_app_country] => US [patent_app_date] => 1999-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4748 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341366.pdf [firstpage_image] =>[orig_patent_app_number] => 09232467 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/232467
Rule-driven method and system for editing physical integrated circuit layouts Jan 14, 1999 Issued
Array ( [id] => 4423856 [patent_doc_number] => 06311313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'X-Y grid tree clock distribution network with tunable tree and grid networks' [patent_app_type] => 1 [patent_app_number] => 9/222141 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6995 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311313.pdf [firstpage_image] =>[orig_patent_app_number] => 222141 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222141
X-Y grid tree clock distribution network with tunable tree and grid networks Dec 28, 1998 Issued
Array ( [id] => 7638551 [patent_doc_number] => 06397370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method and system for breaking complex Boolean networks' [patent_app_type] => B1 [patent_app_number] => 09/216357 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5166 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397370.pdf [firstpage_image] =>[orig_patent_app_number] => 09216357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/216357
Method and system for breaking complex Boolean networks Dec 17, 1998 Issued
Array ( [id] => 1501809 [patent_doc_number] => 06405354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method and apparatus to optimize power wiring layout and generate wiring layout data for a semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/215239 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 5021 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405354.pdf [firstpage_image] =>[orig_patent_app_number] => 09215239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/215239
Method and apparatus to optimize power wiring layout and generate wiring layout data for a semiconductor integrated circuit Dec 17, 1998 Issued
Array ( [id] => 1587633 [patent_doc_number] => 06425110 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Incremental design tuning and decision mediator' [patent_app_type] => B1 [patent_app_number] => 09/213675 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10572 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425110.pdf [firstpage_image] =>[orig_patent_app_number] => 09213675 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213675
Incremental design tuning and decision mediator Dec 16, 1998 Issued
Array ( [id] => 1472140 [patent_doc_number] => 06460166 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'System and method for restructuring of logic circuitry' [patent_app_type] => B1 [patent_app_number] => 09/213322 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 5521 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460166.pdf [firstpage_image] =>[orig_patent_app_number] => 09213322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213322
System and method for restructuring of logic circuitry Dec 15, 1998 Issued
Array ( [id] => 4412898 [patent_doc_number] => 06298466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method and system for synthesizing operational amplifiers for amplifying systems with minimal total harmonic distortion' [patent_app_type] => 1 [patent_app_number] => 9/206747 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6154 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298466.pdf [firstpage_image] =>[orig_patent_app_number] => 206747 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206747
Method and system for synthesizing operational amplifiers for amplifying systems with minimal total harmonic distortion Dec 6, 1998 Issued
Array ( [id] => 4374915 [patent_doc_number] => 06292927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Reduction of process antenna effects in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/207159 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6023 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292927.pdf [firstpage_image] =>[orig_patent_app_number] => 207159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207159
Reduction of process antenna effects in integrated circuits Dec 6, 1998 Issued
Array ( [id] => 1549888 [patent_doc_number] => 06374396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Correction of field effects in photolithography' [patent_app_type] => B1 [patent_app_number] => 09/205896 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5236 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 47 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374396.pdf [firstpage_image] =>[orig_patent_app_number] => 09205896 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205896
Correction of field effects in photolithography Dec 3, 1998 Issued
Array ( [id] => 4412975 [patent_doc_number] => 06298473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Apparatus and method for inhibiting pattern distortions to correct pattern data in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/204281 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 6412 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298473.pdf [firstpage_image] =>[orig_patent_app_number] => 204281 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204281
Apparatus and method for inhibiting pattern distortions to correct pattern data in a semiconductor device Dec 2, 1998 Issued
Array ( [id] => 4424405 [patent_doc_number] => 06301688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Insertion of test points in RTL designs' [patent_app_type] => 1 [patent_app_number] => 9/199018 [patent_app_country] => US [patent_app_date] => 1998-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4480 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301688.pdf [firstpage_image] =>[orig_patent_app_number] => 199018 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/199018
Insertion of test points in RTL designs Nov 23, 1998 Issued
Array ( [id] => 1526618 [patent_doc_number] => 06353920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Method for implementing wide gates and tristate buffers using FPGA carry logic' [patent_app_type] => B1 [patent_app_number] => 09/193283 [patent_app_country] => US [patent_app_date] => 1998-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5758 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353920.pdf [firstpage_image] =>[orig_patent_app_number] => 09193283 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193283
Method for implementing wide gates and tristate buffers using FPGA carry logic Nov 16, 1998 Issued
Array ( [id] => 4153428 [patent_doc_number] => 06148433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Systematic approach for regularity extraction' [patent_app_type] => 1 [patent_app_number] => 9/187543 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 8538 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148433.pdf [firstpage_image] =>[orig_patent_app_number] => 187543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187543
Systematic approach for regularity extraction Nov 5, 1998 Issued
09/192177 METHOD AND APPARATUS FOR GENERATING PACKAGE GEOMETRIES Oct 29, 1998 Abandoned
Array ( [id] => 4380534 [patent_doc_number] => 06192509 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method and apparatus for automatically removing acid traps from a hatched fill in a printed circuit board design' [patent_app_type] => 1 [patent_app_number] => 9/178165 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 4358 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192509.pdf [firstpage_image] =>[orig_patent_app_number] => 178165 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178165
Method and apparatus for automatically removing acid traps from a hatched fill in a printed circuit board design Oct 22, 1998 Issued
Array ( [id] => 7638547 [patent_doc_number] => 06397374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Zero hold time circuit for high speed bus applications' [patent_app_type] => B1 [patent_app_number] => 09/164218 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5862 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397374.pdf [firstpage_image] =>[orig_patent_app_number] => 09164218 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164218
Zero hold time circuit for high speed bus applications Sep 29, 1998 Issued
Array ( [id] => 4336164 [patent_doc_number] => 06243855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Mask data design method' [patent_app_type] => 1 [patent_app_number] => 9/161959 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 8448 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243855.pdf [firstpage_image] =>[orig_patent_app_number] => 161959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/161959
Mask data design method Sep 28, 1998 Issued
Array ( [id] => 4424411 [patent_doc_number] => 06301689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Spacing violation checker' [patent_app_type] => 1 [patent_app_number] => 9/162215 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3434 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301689.pdf [firstpage_image] =>[orig_patent_app_number] => 162215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162215
Spacing violation checker Sep 27, 1998 Issued
Array ( [id] => 4347387 [patent_doc_number] => 06330707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Automatic routing method' [patent_app_type] => 1 [patent_app_number] => 9/157387 [patent_app_country] => US [patent_app_date] => 1998-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 10272 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330707.pdf [firstpage_image] =>[orig_patent_app_number] => 157387 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/157387
Automatic routing method Sep 20, 1998 Issued
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