Search

Vicki B. Booker

Examiner (ID: 13967, Phone: (571)270-1565 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2821, 2813, 2893
Total Applications
782
Issued Applications
655
Pending Applications
6
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11446408 [patent_doc_number] => 20170047429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'ASYMMETRIC SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/338667 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338667 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338667
Method of forming semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric Oct 30, 2016 Issued
Array ( [id] => 11439308 [patent_doc_number] => 20170040329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'METHOD FOR PRODUCING AN SGT-INCLUDING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/285665 [patent_app_country] => US [patent_app_date] => 2016-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 18550 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15285665 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/285665
METHOD FOR PRODUCING AN SGT-INCLUDING SEMICONDUCTOR DEVICE Oct 4, 2016 Abandoned
Array ( [id] => 11608212 [patent_doc_number] => 20170125516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/272993 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6052 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272993 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272993
Gallium nitride based high electron mobility transistor (GaN-HEMT) device with an iron-doped cap layer and method of manufacturing the same Sep 21, 2016 Issued
Array ( [id] => 12263763 [patent_doc_number] => 20180082959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 15/272838 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6272 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272838 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272838
Wafer level integration including design/co-design, structure process, equipment stress management and thermal management Sep 21, 2016 Issued
Array ( [id] => 15427793 [patent_doc_number] => 10546836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Wafer level integration including design/co-design, structure process, equipment stress management and thermal management [patent_app_type] => utility [patent_app_number] => 15/272804 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 6103 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272804 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272804
Wafer level integration including design/co-design, structure process, equipment stress management and thermal management Sep 21, 2016 Issued
Array ( [id] => 12535008 [patent_doc_number] => 10008528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Solid-state image sensor, method of manufacturing the same, and camera [patent_app_type] => utility [patent_app_number] => 15/272738 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 7434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272738 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272738
Solid-state image sensor, method of manufacturing the same, and camera Sep 21, 2016 Issued
Array ( [id] => 16386460 [patent_doc_number] => 10811305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Wafer level integration including design/co-design, structure process, equipment stress management, and thermal management [patent_app_type] => utility [patent_app_number] => 15/272758 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 6071 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272758 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272758
Wafer level integration including design/co-design, structure process, equipment stress management, and thermal management Sep 21, 2016 Issued
Array ( [id] => 12574314 [patent_doc_number] => 10020366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Removal of basal plane dislocations from silicon carbide substrate surface by high temperature annealing and preserving surface morphology [patent_app_type] => utility [patent_app_number] => 15/272736 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272736 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272736
Removal of basal plane dislocations from silicon carbide substrate surface by high temperature annealing and preserving surface morphology Sep 21, 2016 Issued
Array ( [id] => 11367030 [patent_doc_number] => 20170005011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'FINFET Devices and Methods of Forming' [patent_app_type] => utility [patent_app_number] => 15/268837 [patent_app_country] => US [patent_app_date] => 2016-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15268837 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/268837
FinFET devices and methods of forming Sep 18, 2016 Issued
Array ( [id] => 12223282 [patent_doc_number] => 20180061642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/253074 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253074 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/253074
Method of manufacturing a semiconductor device including a ternary alloy layer formed by a microwafe anneal process Aug 30, 2016 Issued
Array ( [id] => 12223339 [patent_doc_number] => 20180061699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'MULTIPLE PATTERNING PROCESS FOR FORMING PILLAR MASK ELEMENTS' [patent_app_type] => utility [patent_app_number] => 15/253097 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3149 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253097 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/253097
Multiple patterning process for forming pillar mask elements Aug 30, 2016 Issued
Array ( [id] => 11959459 [patent_doc_number] => 20170263611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/253816 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253816 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/253816
Method of manufacturing 3-dimensional memories including high aspect ratio memory hole patterns Aug 30, 2016 Issued
Array ( [id] => 12223267 [patent_doc_number] => 20180061628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'SELECTIVE ATOMIC LAYER DEPOSITION FOR GAPFILL USING SACRIFICIAL UNDERLAYER' [patent_app_type] => utility [patent_app_number] => 15/253301 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253301 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/253301
Selective atomic layer deposition for gapfill using sacrificial underlayer Aug 30, 2016 Issued
Array ( [id] => 13111771 [patent_doc_number] => 10074543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => High dry etch rate materials for semiconductor patterning applications [patent_app_type] => utility [patent_app_number] => 15/253546 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10822 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/253546
High dry etch rate materials for semiconductor patterning applications Aug 30, 2016 Issued
Array ( [id] => 11524651 [patent_doc_number] => 09608062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-28 [patent_title] => 'Semiconductor structure and method of forming the same' [patent_app_type] => utility [patent_app_number] => 15/250924 [patent_app_country] => US [patent_app_date] => 2016-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15250924 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/250924
Semiconductor structure and method of forming the same Aug 29, 2016 Issued
Array ( [id] => 11946102 [patent_doc_number] => 20170250253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'SEMICONDUCTOR DEVICE WITH BURIED CONDUCTIVE REGION, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/250638 [patent_app_country] => US [patent_app_date] => 2016-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15250638 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/250638
Semiconductor device with buried metallic region, and method for manufacturing the semiconductor device Aug 28, 2016 Issued
Array ( [id] => 11328431 [patent_doc_number] => 20160359042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND A METHOD OF MANUFACTURING SAME USING DUMMY GATE PROCESS' [patent_app_type] => utility [patent_app_number] => 15/236933 [patent_app_country] => US [patent_app_date] => 2016-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 21706 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236933 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236933
Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process Aug 14, 2016 Issued
Array ( [id] => 12047321 [patent_doc_number] => 09824930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme' [patent_app_type] => utility [patent_app_number] => 15/232895 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 7906 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232895 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/232895
Method of patterning dopant films in high-k dielectrics in a soft mask integration scheme Aug 9, 2016 Issued
Array ( [id] => 13335189 [patent_doc_number] => 20180219132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT [patent_app_type] => utility [patent_app_number] => 15/747728 [patent_app_country] => US [patent_app_date] => 2016-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15747728 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/747728
Optoelectronic component with electrically-conductive adhesive layer including titanium oxide and method for producing the optoelectronic component Aug 2, 2016 Issued
Array ( [id] => 11475638 [patent_doc_number] => 20170062420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/222300 [patent_app_country] => US [patent_app_date] => 2016-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 19667 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15222300 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/222300
SEMICONDUCTOR DEVICE Jul 27, 2016 Abandoned
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