Vicki B. Booker

Array ( [id] => 8446762 [patent_doc_number] => 08288817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Semiconductor constructions for transistor gates and NAND cell units' [patent_app_type] => utility [patent_app_number] => 12/986487 [patent_app_country] => US [patent_app_date] => 2011-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12986487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10837920 [patent_doc_number] => 08865591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'N-type contact electrode formed on an N-type semiconductor layer and method of forming same using a second metal electrode layer heat-treated after being formed on a first, heat-treated metal electrode layer' [patent_app_type] => utility [patent_app_number] => 13/517260 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10627 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13517260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5989230 [patent_doc_number] => 20110012192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'Vertical Channel Transistor Structure and Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/892044 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3644 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20110012192.pdf [firstpage_image] =>[orig_patent_app_number] => 12892044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9009231 [patent_doc_number] => 08524527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'High-performance single-crystalline N-type dopant-doped metal oxide nanowires for transparent thin film transistors and active matrix organic light-emitting diode displays' [patent_app_type] => utility [patent_app_number] => 12/891764 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 6637 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12891764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9455072 [patent_doc_number] => 08716079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Superior fill conditions in a replacement gate approach by corner rounding based on a sacrificial fill material' [patent_app_type] => utility [patent_app_number] => 12/891403 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 8004 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12891403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9850755 [patent_doc_number] => 08952490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Redox capacitor and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/891461 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4932 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12891461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8049613 [patent_doc_number] => 20120074534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Semiconductor Device and Method of Forming Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer' [patent_app_type] => utility [patent_app_number] => 12/891232 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5705 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20120074534.pdf [firstpage_image] =>[orig_patent_app_number] => 12891232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5980009 [patent_doc_number] => 20110095313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/891731 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20110095313.pdf [firstpage_image] =>[orig_patent_app_number] => 12891731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6114428 [patent_doc_number] => 20110073959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'STRESS ENGINEERING IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES BY STRESSED CONDUCTIVE LAYERS AND AN ISOLATION SPACER' [patent_app_type] => utility [patent_app_number] => 12/891301 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8497 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20110073959.pdf [firstpage_image] =>[orig_patent_app_number] => 12891301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9233378 [patent_doc_number] => 08598686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Electronic device package structure with a hydrophilic protection layer and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/891734 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3295 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12891734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8049547 [patent_doc_number] => 20120074506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Semiconductor Package for Higher Power Transistors' [patent_app_type] => utility [patent_app_number] => 12/891576 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3185 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20120074506.pdf [firstpage_image] =>[orig_patent_app_number] => 12891576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9086218 [patent_doc_number] => 08557645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Semiconductor device with a gate electrode having a shape formed based on a slope and gate lower opening and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/875506 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 34 [patent_no_of_words] => 11377 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12875506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6265561 [patent_doc_number] => 20100297839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING MULTIPLE GATE INSULATING LAYER' [patent_app_type] => utility [patent_app_number] => 12/850974 [patent_app_country] => US [patent_app_date] => 2010-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5385 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20100297839.pdf [firstpage_image] =>[orig_patent_app_number] => 12850974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9153563 [patent_doc_number] => 08586469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Metal layer end-cut flow' [patent_app_type] => utility [patent_app_number] => 12/845448 [patent_app_country] => US [patent_app_date] => 2010-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12845448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9232671 [patent_doc_number] => 08597974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Confined resistance variable memory cells and methods' [patent_app_type] => utility [patent_app_number] => 12/843640 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3846 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12843640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6445607 [patent_doc_number] => 20100283094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/840599 [patent_app_country] => US [patent_app_date] => 2010-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7856 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20100283094.pdf [firstpage_image] =>[orig_patent_app_number] => 12840599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7518773 [patent_doc_number] => 07972874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Semiconductor process evaluation methods including variable ion implanting conditions' [patent_app_type] => utility [patent_app_number] => 12/834201 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 6450 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/972/07972874.pdf [firstpage_image] =>[orig_patent_app_number] => 12834201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9323487 [patent_doc_number] => 08658507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'MOSFET structure and method of fabricating the same using replacement channel layer' [patent_app_type] => utility [patent_app_number] => 12/990714 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 4426 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12990714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9074910 [patent_doc_number] => 08552490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Nonvolatile memory device with a high-K charge storage layer having a U-shaped,cross-sectional structure' [patent_app_type] => utility [patent_app_number] => 12/818176 [patent_app_country] => US [patent_app_date] => 2010-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3858 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12818176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6153781 [patent_doc_number] => 20110156251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'Semiconductor Package' [patent_app_type] => utility [patent_app_number] => 12/818422 [patent_app_country] => US [patent_app_date] => 2010-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2055 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20110156251.pdf [firstpage_image] =>[orig_patent_app_number] => 12818422 [rel_patent_id] =>[rel_patent_doc_number] =>)