Search

Vicki B. Booker

Examiner (ID: 4517, Phone: (571)270-1565 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2821, 2893
Total Applications
782
Issued Applications
655
Pending Applications
6
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5834811 [patent_doc_number] => 20060246642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'SEMICONDUCTOR POWER DEVICE WITH PASSIVATION LAYERS' [patent_app_type] => utility [patent_app_number] => 11/380466 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3057 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20060246642.pdf [firstpage_image] =>[orig_patent_app_number] => 11380466 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/380466
Semiconductor power device with passivation layers Apr 26, 2006 Issued
Array ( [id] => 236258 [patent_doc_number] => 07595239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Method of fabricating flash memory device' [patent_app_type] => utility [patent_app_number] => 11/380416 [patent_app_country] => US [patent_app_date] => 2006-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 2413 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595239.pdf [firstpage_image] =>[orig_patent_app_number] => 11380416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/380416
Method of fabricating flash memory device Apr 25, 2006 Issued
Array ( [id] => 5680829 [patent_doc_number] => 20060197096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Substrate with refractive index matching' [patent_app_type] => utility [patent_app_number] => 11/412215 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4038 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20060197096.pdf [firstpage_image] =>[orig_patent_app_number] => 11412215 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/412215
Substrate with refractive index matching Apr 24, 2006 Abandoned
Array ( [id] => 5210528 [patent_doc_number] => 20070249112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'DIFFERENTIAL SPACER FORMATION FOR A FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/308686 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20070249112.pdf [firstpage_image] =>[orig_patent_app_number] => 11308686 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308686
DIFFERENTIAL SPACER FORMATION FOR A FIELD EFFECT TRANSISTOR Apr 20, 2006 Abandoned
Array ( [id] => 5210544 [patent_doc_number] => 20070249128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Ultraviolet (UV) Radiation Treatment Methods for Subatmospheric Chemical Vapor Deposition (SACVD) of Ozone-Tetraethoxysilane (O3-TEOS)' [patent_app_type] => utility [patent_app_number] => 11/379285 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4467 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20070249128.pdf [firstpage_image] =>[orig_patent_app_number] => 11379285 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/379285
Ultraviolet (UV) Radiation Treatment Methods for Subatmospheric Chemical Vapor Deposition (SACVD) of Ozone-Tetraethoxysilane (O3-TEOS) Apr 18, 2006 Abandoned
Array ( [id] => 5210494 [patent_doc_number] => 20070249078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Non-planar surface structures and process for microelectromechanical systems' [patent_app_type] => utility [patent_app_number] => 11/406776 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11787 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20070249078.pdf [firstpage_image] =>[orig_patent_app_number] => 11406776 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/406776
Non-planar surface structures and process for microelectromechanical systems Apr 18, 2006 Abandoned
Array ( [id] => 5205109 [patent_doc_number] => 20070026591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Insulated gate field effect transistor having passivated schottky barriers to the channel' [patent_app_type] => utility [patent_app_number] => 11/403185 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9152 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20070026591.pdf [firstpage_image] =>[orig_patent_app_number] => 11403185 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/403185
Insulated gate field effect transistor having passivated schottky barriers to the channel Apr 10, 2006 Issued
Array ( [id] => 5126033 [patent_doc_number] => 20070238304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'METHOD OF ETCHING PASSIVATION LAYER' [patent_app_type] => utility [patent_app_number] => 11/279255 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2409 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20070238304.pdf [firstpage_image] =>[orig_patent_app_number] => 11279255 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/279255
METHOD OF ETCHING PASSIVATION LAYER Apr 10, 2006 Abandoned
Array ( [id] => 5625561 [patent_doc_number] => 20060264066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Multilayer multicomponent high-k films and methods for depositing the same' [patent_app_type] => utility [patent_app_number] => 11/400366 [patent_app_country] => US [patent_app_date] => 2006-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7462 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20060264066.pdf [firstpage_image] =>[orig_patent_app_number] => 11400366 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/400366
Multilayer multicomponent high-k films and methods for depositing the same Apr 6, 2006 Abandoned
Array ( [id] => 5126035 [patent_doc_number] => 20070238306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'METHOD OF FORMING DUAL DAMASCENE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/279055 [patent_app_country] => US [patent_app_date] => 2006-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20070238306.pdf [firstpage_image] =>[orig_patent_app_number] => 11279055 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/279055
Method of forming dual damascene semiconductor device Apr 6, 2006 Issued
Array ( [id] => 7801020 [patent_doc_number] => 08129290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Method to increase tensile stress of silicon nitride films using a post PECVD deposition UV cure' [patent_app_type] => utility [patent_app_number] => 11/400275 [patent_app_country] => US [patent_app_date] => 2006-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 90 [patent_no_of_words] => 19026 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129290.pdf [firstpage_image] =>[orig_patent_app_number] => 11400275 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/400275
Method to increase tensile stress of silicon nitride films using a post PECVD deposition UV cure Apr 6, 2006 Issued
Array ( [id] => 5123527 [patent_doc_number] => 20070235797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Process for reducing a size of a compact EEPROM device' [patent_app_type] => utility [patent_app_number] => 11/393145 [patent_app_country] => US [patent_app_date] => 2006-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4040 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20070235797.pdf [firstpage_image] =>[orig_patent_app_number] => 11393145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/393145
Process for reducing a size of a compact EEPROM device Mar 28, 2006 Abandoned
Array ( [id] => 7515319 [patent_doc_number] => 08039391 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-18 [patent_title] => 'Method of forming a contact in a semiconductor device with engineered plasma treatment profile of barrier metal layer' [patent_app_type] => utility [patent_app_number] => 11/388976 [patent_app_country] => US [patent_app_date] => 2006-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3388 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/039/08039391.pdf [firstpage_image] =>[orig_patent_app_number] => 11388976 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/388976
Method of forming a contact in a semiconductor device with engineered plasma treatment profile of barrier metal layer Mar 26, 2006 Issued
Array ( [id] => 5694336 [patent_doc_number] => 20060154483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'METHOD OF PROVIDING A STRUCTURE USING SELF-ALIGNED FEATURES' [patent_app_type] => utility [patent_app_number] => 11/277340 [patent_app_country] => US [patent_app_date] => 2006-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4326 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20060154483.pdf [firstpage_image] =>[orig_patent_app_number] => 11277340 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/277340
METHOD OF PROVIDING A STRUCTURE USING SELF-ALIGNED FEATURES Mar 22, 2006 Abandoned
Array ( [id] => 5685916 [patent_doc_number] => 20060284231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Dielectric memory and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/384245 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10526 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20060284231.pdf [firstpage_image] =>[orig_patent_app_number] => 11384245 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/384245
Dielectric memory and method for manufacturing the same Mar 20, 2006 Abandoned
Array ( [id] => 5655922 [patent_doc_number] => 20060141658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'CORRUGATED DIAPHRAGM' [patent_app_type] => utility [patent_app_number] => 11/276596 [patent_app_country] => US [patent_app_date] => 2006-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3002 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20060141658.pdf [firstpage_image] =>[orig_patent_app_number] => 11276596 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/276596
CORRUGATED DIAPHRAGM Mar 6, 2006 Abandoned
Array ( [id] => 224863 [patent_doc_number] => 07605046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'Active matrix structure for a display device and method for its manufacture' [patent_app_type] => utility [patent_app_number] => 11/358475 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2198 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/605/07605046.pdf [firstpage_image] =>[orig_patent_app_number] => 11358475 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358475
Active matrix structure for a display device and method for its manufacture Feb 20, 2006 Issued
Array ( [id] => 5652812 [patent_doc_number] => 20060138547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection' [patent_app_type] => utility [patent_app_number] => 11/356256 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8569 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138547.pdf [firstpage_image] =>[orig_patent_app_number] => 11356256 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/356256
Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection Feb 15, 2006 Issued
Array ( [id] => 5217428 [patent_doc_number] => 20070158739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Higher performance CMOS on (110) wafers' [patent_app_type] => utility [patent_app_number] => 11/327256 [patent_app_country] => US [patent_app_date] => 2006-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20070158739.pdf [firstpage_image] =>[orig_patent_app_number] => 11327256 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/327256
Higher performance CMOS on (110) wafers Jan 5, 2006 Abandoned
Array ( [id] => 314768 [patent_doc_number] => 07524738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/321539 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1473 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/524/07524738.pdf [firstpage_image] =>[orig_patent_app_number] => 11321539 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/321539
Method for manufacturing semiconductor device Dec 29, 2005 Issued
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