Search

Victor A. Mandala

Examiner (ID: 6003, Phone: (571)272-1918 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2826, 2899
Total Applications
2126
Issued Applications
1923
Pending Applications
101
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15939111 [patent_doc_number] => 20200161189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => SELF-ALIGNED QUADRUPLE PATTERNING PROCESS FOR FIN PITCH BELOW 20nm [patent_app_type] => utility [patent_app_number] => 16/752157 [patent_app_country] => US [patent_app_date] => 2020-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752157 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/752157
SELF-ALIGNED QUADRUPLE PATTERNING PROCESS FOR FIN PITCH BELOW 20nm Jan 23, 2020 Abandoned
Array ( [id] => 16715645 [patent_doc_number] => 20210082792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => ELECTRICAL DEVICE WITH TERMINAL NOTCHES AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/661384 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661384
ELECTRICAL DEVICE WITH TERMINAL NOTCHES AND METHOD FOR MANUFACTURING THE SAME Oct 22, 2019 Abandoned
Array ( [id] => 17438924 [patent_doc_number] => 11264264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Solder bump formation using wafer with ring [patent_app_type] => utility [patent_app_number] => 16/661686 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 5774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661686 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661686
Solder bump formation using wafer with ring Oct 22, 2019 Issued
Array ( [id] => 17332393 [patent_doc_number] => 11222861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Dual-interface IC card module [patent_app_type] => utility [patent_app_number] => 16/523442 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 6718 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523442 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523442
Dual-interface IC card module Jul 25, 2019 Issued
Array ( [id] => 17559109 [patent_doc_number] => 11315831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Dual redistribution layer structure [patent_app_type] => utility [patent_app_number] => 16/518166 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6762 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518166 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518166
Dual redistribution layer structure Jul 21, 2019 Issued
Array ( [id] => 17224694 [patent_doc_number] => 11177204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Power electronics package and method of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 16/448691 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 7252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16448691 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/448691
Power electronics package and method of manufacturing thereof Jun 20, 2019 Issued
Array ( [id] => 14691837 [patent_doc_number] => 20190245034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/387243 [patent_app_country] => US [patent_app_date] => 2019-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16387243 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/387243
Power device integration on a common substrate Apr 16, 2019 Issued
Array ( [id] => 15332563 [patent_doc_number] => 20200006611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 16/359470 [patent_app_country] => US [patent_app_date] => 2019-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16359470 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/359470
Light emitting device Mar 19, 2019 Issued
Array ( [id] => 16707691 [patent_doc_number] => 10957635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Multi-chip package with high thermal conductivity die attach [patent_app_type] => utility [patent_app_number] => 16/359628 [patent_app_country] => US [patent_app_date] => 2019-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2526 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16359628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/359628
Multi-chip package with high thermal conductivity die attach Mar 19, 2019 Issued
Array ( [id] => 15532731 [patent_doc_number] => 20200058671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => VERTICAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/270570 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -45 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270570 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/270570
Vertical memory device Feb 6, 2019 Issued
Array ( [id] => 17284080 [patent_doc_number] => 11201122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Method of fabricating semiconductor device with reduced warpage and better trench filling performance [patent_app_type] => utility [patent_app_number] => 16/270477 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7249 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/270477
Method of fabricating semiconductor device with reduced warpage and better trench filling performance Feb 6, 2019 Issued
Array ( [id] => 16241604 [patent_doc_number] => 20200258838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => SYSTEMS AND METHODS FOR SCALE OUT INTEGRATION OF CHIPS [patent_app_type] => utility [patent_app_number] => 16/270311 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/270311
SYSTEMS AND METHODS FOR SCALE OUT INTEGRATION OF CHIPS Feb 6, 2019 Abandoned
Array ( [id] => 14284955 [patent_doc_number] => 20190139762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => EPITAXIAL GROWTH OF DEFECT-FREE, WAFER-SCALE SINGLE-LAYER GRAPHENE ON THIN FILMS OF COBALT [patent_app_type] => utility [patent_app_number] => 16/234711 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234711 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/234711
EPITAXIAL GROWTH OF DEFECT-FREE, WAFER-SCALE SINGLE-LAYER GRAPHENE ON THIN FILMS OF COBALT Dec 27, 2018 Abandoned
Array ( [id] => 14317121 [patent_doc_number] => 20190148264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => Wafer Level Embedded Heat Spreader [patent_app_type] => utility [patent_app_number] => 16/231783 [patent_app_country] => US [patent_app_date] => 2018-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/231783
Wafer level embedded heat spreader Dec 23, 2018 Issued
Array ( [id] => 16417837 [patent_doc_number] => 10825738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Semiconductor arrangements and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/222570 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 42 [patent_no_of_words] => 9839 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222570 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/222570
Semiconductor arrangements and methods of manufacturing the same Dec 16, 2018 Issued
Array ( [id] => 14476281 [patent_doc_number] => 20190189789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => IGBT with Fully Depletable n- and p-Channel Regions [patent_app_type] => utility [patent_app_number] => 16/220130 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220130 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220130
IGBT with fully depletable n- and p-channel regions Dec 13, 2018 Issued
Array ( [id] => 16081119 [patent_doc_number] => 20200194546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => TECHNIQUES FOR FABRICATING PLANAR CHARGE BALANCED (CB) METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) DEVICES [patent_app_type] => utility [patent_app_number] => 16/221034 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221034 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/221034
Techniques for fabricating planar charge balanced (CB) metal-oxide-semiconductor field-effect transistor (MOSFET) devices Dec 13, 2018 Issued
Array ( [id] => 14476281 [patent_doc_number] => 20190189789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => IGBT with Fully Depletable n- and p-Channel Regions [patent_app_type] => utility [patent_app_number] => 16/220130 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220130 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220130
IGBT with fully depletable n- and p-channel regions Dec 13, 2018 Issued
Array ( [id] => 14476281 [patent_doc_number] => 20190189789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => IGBT with Fully Depletable n- and p-Channel Regions [patent_app_type] => utility [patent_app_number] => 16/220130 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220130 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220130
IGBT with fully depletable n- and p-channel regions Dec 13, 2018 Issued
Array ( [id] => 14476281 [patent_doc_number] => 20190189789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => IGBT with Fully Depletable n- and p-Channel Regions [patent_app_type] => utility [patent_app_number] => 16/220130 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220130 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220130
IGBT with fully depletable n- and p-channel regions Dec 13, 2018 Issued
Menu