Search

Victor A. Mandala

Examiner (ID: 2078, Phone: (571)272-1918 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2899, 2826
Total Applications
2162
Issued Applications
1946
Pending Applications
107
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19007406 [patent_doc_number] => 20240071477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/500478 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 511 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18500478 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/500478
Memory system Nov 1, 2023 Issued
Array ( [id] => 19646236 [patent_doc_number] => 20240420756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => MEMORY AND ITS OPERATION METHODS, MEMORY SYSTEMS, AND ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/488961 [patent_app_country] => US [patent_app_date] => 2023-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/488961
Memory and its operation methods, memory systems, and electronic devices Oct 16, 2023 Issued
Array ( [id] => 19634327 [patent_doc_number] => 20240412776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => MEMORY DEVICE INCLUDING A PAGE BUFFER [patent_app_type] => utility [patent_app_number] => 18/483525 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483525 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483525
MEMORY DEVICE INCLUDING A PAGE BUFFER Oct 9, 2023 Pending
Array ( [id] => 20375075 [patent_doc_number] => 12482517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => DRAM device and ODT resistor value adjustment method and computer program for the same [patent_app_type] => utility [patent_app_number] => 18/476475 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18476475 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/476475
DRAM device and ODT resistor value adjustment method and computer program for the same Sep 27, 2023 Issued
Array ( [id] => 19943411 [patent_doc_number] => 12315547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Refresh operation in multi-die memory [patent_app_type] => utility [patent_app_number] => 18/373120 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2323 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373120 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/373120
Refresh operation in multi-die memory Sep 25, 2023 Issued
Array ( [id] => 19054426 [patent_doc_number] => 20240096395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => DEVICE, OPERATING METHOD, MEMORY DEVICE, AND CXL MEMORY EXPANSION DEVICE [patent_app_type] => utility [patent_app_number] => 18/470471 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470471 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470471
Device, operating method, memory device, and CXL memory expansion device Sep 19, 2023 Issued
Array ( [id] => 19886693 [patent_doc_number] => 12272418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Performing select gate integrity checks to identify and invalidate defective blocks [patent_app_type] => utility [patent_app_number] => 18/242884 [patent_app_country] => US [patent_app_date] => 2023-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18242884 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/242884
Performing select gate integrity checks to identify and invalidate defective blocks Sep 5, 2023 Issued
Array ( [id] => 20416637 [patent_doc_number] => 12499926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Semiconductor device capable of switching operation voltage [patent_app_type] => utility [patent_app_number] => 18/460992 [patent_app_country] => US [patent_app_date] => 2023-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18460992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/460992
Semiconductor device capable of switching operation voltage Sep 4, 2023 Issued
Array ( [id] => 20266802 [patent_doc_number] => 12437798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Voltage regulator and memory device [patent_app_type] => utility [patent_app_number] => 18/459453 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459453 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/459453
Voltage regulator and memory device Aug 31, 2023 Issued
Array ( [id] => 19252487 [patent_doc_number] => 20240203484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/459066 [patent_app_country] => US [patent_app_date] => 2023-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459066 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/459066
Memory device Aug 30, 2023 Issued
Array ( [id] => 18848487 [patent_doc_number] => 20230410891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => MEMORY DEVICE TRANSMITTING AND RECEIVING DATA AT HIGH SPEED AND LOW POWER [patent_app_type] => utility [patent_app_number] => 18/458743 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/458743
Memory device transmitting and receiving data at high speed and low power Aug 29, 2023 Issued
Array ( [id] => 18833548 [patent_doc_number] => 20230402075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/451946 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451946
Memory device Aug 17, 2023 Issued
Array ( [id] => 20434206 [patent_doc_number] => 12504887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Erase and program operations for memory devices having multiple storage modes [patent_app_type] => utility [patent_app_number] => 18/451769 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 12931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451769
Erase and program operations for memory devices having multiple storage modes Aug 16, 2023 Issued
Array ( [id] => 20416642 [patent_doc_number] => 12499931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Memory device having segmented data line structure [patent_app_type] => utility [patent_app_number] => 18/448525 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448525 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448525
Memory device having segmented data line structure Aug 10, 2023 Issued
Array ( [id] => 19775359 [patent_doc_number] => 20250056785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => STRUCTURES OF SRAM CELL AND METHODS OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/366471 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366471 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366471
Structures of sram cell and methods of fabricating the same Aug 6, 2023 Issued
Array ( [id] => 20596312 [patent_doc_number] => 12580035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Memory module with reduced ECC overhead and memory system [patent_app_type] => utility [patent_app_number] => 18/365868 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 4509 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365868 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365868
Memory module with reduced ECC overhead and memory system Aug 3, 2023 Issued
Array ( [id] => 20191158 [patent_doc_number] => 12402296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Semiconductor element memory device [patent_app_type] => utility [patent_app_number] => 18/228852 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 36 [patent_no_of_words] => 6447 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 466 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228852
Semiconductor element memory device Jul 31, 2023 Issued
Array ( [id] => 19943422 [patent_doc_number] => 12315558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Semiconductor element memory device [patent_app_type] => utility [patent_app_number] => 18/228433 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 30 [patent_no_of_words] => 5617 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 442 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228433 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228433
Semiconductor element memory device Jul 30, 2023 Issued
Array ( [id] => 19618925 [patent_doc_number] => 20240404605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => ESTIMATING PEAK SOURCE CURRENT USING MEMORY DIE SUBSTRATE TEMPERATURE DETECTION [patent_app_type] => utility [patent_app_number] => 18/358763 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358763 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358763
Estimating peak source current using memory die substrate temperature detection Jul 24, 2023 Issued
Array ( [id] => 20455756 [patent_doc_number] => 12518816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Write duty cycle calibration on a memory device [patent_app_type] => utility [patent_app_number] => 18/225878 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225878 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225878
Write duty cycle calibration on a memory device Jul 24, 2023 Issued
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