Search

Victor V. Barzykin

Examiner (ID: 15522, Phone: (571)272-0508 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2821, 2893, 2822
Total Applications
541
Issued Applications
412
Pending Applications
56
Abandoned Applications
84

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19515784 [patent_doc_number] => 20240347470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => BONDING STRUCTURE, METHOD OF MANUFACTURING THE SAME AND BONDING APPARATUS FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/465982 [patent_app_country] => US [patent_app_date] => 2023-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18465982 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/465982
BONDING STRUCTURE, METHOD OF MANUFACTURING THE SAME AND BONDING APPARATUS FOR MANUFACTURING THE SAME Sep 12, 2023 Pending
Array ( [id] => 18821234 [patent_doc_number] => 20230395575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => METHOD OF TRANSFERRING MICRO-LIGHT EMITTING DIODE FOR LED DISPLAY [patent_app_type] => utility [patent_app_number] => 18/236246 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18236246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/236246
Method of transferring micro-light emitting diode for LED display Aug 20, 2023 Issued
Array ( [id] => 19790095 [patent_doc_number] => 20250063774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => SIC TRENCH DEVICES HAVING N-TYPE GATE OXIDE SHIELD ZONES [patent_app_type] => utility [patent_app_number] => 18/234083 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/234083
SIC TRENCH DEVICES HAVING N-TYPE GATE OXIDE SHIELD ZONES Aug 14, 2023 Pending
Array ( [id] => 20274907 [patent_doc_number] => 12444692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Power module comprising a semiconductor module component and an alignment part, and method for forming the power module [patent_app_type] => utility [patent_app_number] => 19/109527 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 2212 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19109527 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/109527
Power module comprising a semiconductor module component and an alignment part, and method for forming the power module Aug 9, 2023 Issued
Array ( [id] => 19773448 [patent_doc_number] => 20250054874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => THREE-DIMENSIONAL SELF-REFERENCE MARKING FEATURES [patent_app_type] => utility [patent_app_number] => 18/447287 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447287 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447287
THREE-DIMENSIONAL SELF-REFERENCE MARKING FEATURES Aug 8, 2023 Pending
Array ( [id] => 19773447 [patent_doc_number] => 20250054873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING AN ALIGNMENT MARK AND METHODS OF FORMATION [patent_app_type] => utility [patent_app_number] => 18/446299 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446299 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446299
SEMICONDUCTOR DEVICE INCLUDING AN ALIGNMENT MARK AND METHODS OF FORMATION Aug 7, 2023 Pending
Array ( [id] => 19749435 [patent_doc_number] => 20250038000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SiC TRENCH BOTTOM CORNER ROUNDING [patent_app_type] => utility [patent_app_number] => 18/227286 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227286 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227286
SiC TRENCH BOTTOM CORNER ROUNDING Jul 26, 2023 Pending
Array ( [id] => 18812734 [patent_doc_number] => 20230387071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => System and Method for Bonding Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/359416 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359416 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359416
System and method for bonding semiconductor devices Jul 25, 2023 Issued
Array ( [id] => 19071211 [patent_doc_number] => 20240105637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/356238 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356238
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Jul 20, 2023 Pending
Array ( [id] => 18755691 [patent_doc_number] => 20230359135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => OVERLAY MARKS FOR REDUCING EFFECT OF BOTTOM LAYER ASYMMETRY [patent_app_type] => utility [patent_app_number] => 18/356710 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356710 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356710
Overlay marks for reducing effect of bottom layer asymmetry Jul 20, 2023 Issued
Array ( [id] => 19071198 [patent_doc_number] => 20240105624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/356220 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356220 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356220
SEMICONDUCTOR DEVICE Jul 20, 2023 Pending
Array ( [id] => 20516617 [patent_doc_number] => 20260040720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR-METAL CONTACTS OF A SOLAR CELL AND SOLAR CELL [patent_app_type] => utility [patent_app_number] => 18/996491 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18996491 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/996491
METHOD OF MANUFACTURING SEMICONDUCTOR-METAL CONTACTS OF A SOLAR CELL AND SOLAR CELL Jul 13, 2023 Pending
Array ( [id] => 18906078 [patent_doc_number] => 20240021563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => METHOD OF MANUFACTURING A STACKED SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/351748 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351748 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351748
METHOD OF MANUFACTURING A STACKED SEMICONDUCTOR PACKAGE Jul 12, 2023 Pending
Array ( [id] => 18959306 [patent_doc_number] => 20240047633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/347584 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347584
ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF Jul 5, 2023 Pending
Array ( [id] => 19696465 [patent_doc_number] => 20250015010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/218222 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218222 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/218222
SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF Jul 4, 2023 Pending
Array ( [id] => 20979703 [patent_doc_number] => 12740433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-15 [patent_title] => Semiconductor integrated circuit, semiconductor device and method for aligning semiconductor integrated circuits [patent_app_type] => utility [patent_app_number] => 18/346910 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 29 [patent_no_of_words] => 6898 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346910 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346910
SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE AND METHOD FOR ALIGNING SEMICONDUCTOR INTEGRATED CIRCUITS Jul 4, 2023 Pending
Array ( [id] => 19688104 [patent_doc_number] => 20250006649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => DUAL FUNCTIONING ALIGNMENT AND ETCH BIAS STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/216744 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/216744
DUAL FUNCTIONING ALIGNMENT AND ETCH BIAS STRUCTURES Jun 29, 2023 Pending
Array ( [id] => 19260974 [patent_doc_number] => 12021040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Overlay mark forming Moire pattern, overlay measurement method using same, and manufacturing method of semiconductor device using same [patent_app_type] => utility [patent_app_number] => 18/314433 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7842 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 699 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314433 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314433
Overlay mark forming Moire pattern, overlay measurement method using same, and manufacturing method of semiconductor device using same May 8, 2023 Issued
Array ( [id] => 19116448 [patent_doc_number] => 20240128198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => SEMICONDUCTOR WAFER INCLUDING ALIGNMENT KEY PATTERN LAYER INCLUDING CONTACT PATTERN LAYER DISPOSED THEREON [patent_app_type] => utility [patent_app_number] => 18/194656 [patent_app_country] => US [patent_app_date] => 2023-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18194656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/194656
SEMICONDUCTOR WAFER INCLUDING ALIGNMENT KEY PATTERN LAYER INCLUDING CONTACT PATTERN LAYER DISPOSED THEREON Apr 2, 2023 Pending
Array ( [id] => 19146369 [patent_doc_number] => 20240145399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SEMICONDUCTOR WAFER INCLUDING MONITORING PATTERN STRUCTURE WITH COVER PATTERN LAYER AND CONTACT PATTERNS DISPOSED OVER MONITORING PATTERN STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/193637 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193637 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/193637
Semiconductor wafer including monitoring pattern structure with cover pattern layer and contact patterns disposed over monitoring pattern structure Mar 30, 2023 Issued
Menu